clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<whitequark> mwk: and autoidx
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<lambda> mwk: have you started design/coding work on https://github.com/YosysHQ/yosys/issues/1959 yet? I'm wondering if it's worth looking into and getting a feel for it myself or if you're already invested with your own ideas
<tpb> Title: Memory inference redesign · Issue #1959 · YosysHQ/yosys · GitHub (at github.com)
<whitequark> whoo, someone ready to die on that specific hill! i will cheer you on
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<whitequark> more than happy discuss the design as i've spent a while thinking about and discussing it
<ZirconiumX> I've been thinking a lot about it too
<whitequark> particularly around transparency and conversion to verilog
<whitequark> other people might have been focusing on other areas
<lambda> whitequark: I have a month of free time now, might as well try to do something useful ;)
<whitequark> if you fix memory inference you'll have unending gratitude of a lot of people, me included
<lambda> hehe, that alone sounds like a good enough reason to suffer through this alleged mess
<whitequark> good luck. you're going to need it
<whitequark> you'll understand it once you see the code
<lambda> no promises
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