<mwk>
tux3: you can stop bisecting now, I understand the bug
<tux3>
mwk, okay. thanks!
<tux3>
I don't have a repro, but do you still want me to open an issue for it?
<mwk>
*sigh* fuck verilog, seriously
<mwk>
no, I'll take care of it
<tux3>
thanks
<mwk>
want a quick & dirty fix that probably leaves like 100 other instances of the same problem unfixed?
<tux3>
sure, why not
<mwk>
try out the mwk/fix-width-0 branch
<mwk>
(beware: it's untested)
<tux3>
oh wow, that commit is a little frightening. I did not know that was necessary ....
<mwk>
it was not necessary before, because of a bug in verilog frontend
<tux3>
ah
<mwk>
here's a little problem
<mwk>
you cannot have a 0-width wire in verilog
<mwk>
which is quite fucking problematic, because you can in RTLIL
<tux3>
:/
<mwk>
and we're using verilog for converting one cell to another, and the cell you're converting can have 0-width ports, which is *not actually expressible* in Verilog
<mwk>
so the input [A_WIDTH-1:0] A; line actually describes a 2-bit input
<mwk>
(which happen to be A[-1] and A[0])
<mwk>
by passing that down to $pos, which is an internal cell that is strongly validated and expects 0-width input, you get an error
<tux3>
I see
<tux3>
well, your branch seems to work. Or at least, yosys gives no errors
<tux3>
thanks again
<mwk>
alright
<mwk>
I'll try to get it properly fixed tomorrow
<mwk>
there are way more places like that
<mwk>
and yeah, it is a recent regression, PR #2027 specifically
<ZipCPU>
mwk tux3: Is there a zero-length wire something that I need to fix in the crossbar core that I might not know about? Was it the crossbar core causing the problem?
<mwk>
no
<mwk>
there is no way it could be your issue, because you cannot actually make a zero-length wire in verilog
<mwk>
they appear because of yosys optimizations on RTLIL
<mwk>
in this case, on an $alu input
<mwk>
probably some const that got optimized away
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<Forty-Bot>
does yosys allow for some_module #(SOME_PARAMETER = foo) (/* inputs and outputs */) syntax?
<daveshah>
Yes
<daveshah>
If you mean in the module header?
<Forty-Bot>
I mean when instantiating the module
<daveshah>
No you need an instance name between the parameters and ports