clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<sensille> if i had a RAM with rport and one wport, and an additional access to a fixes address (e.g. 0), would yosys be able to infer a single BRAM and duplicate write to that address to a separate register?
<daveshah> No, it would see two read ports and duplicate the BRAM
<sensille> ok, so i have to do that explicitly
<daveshah> Yes
<sensille> what does "Bram port B1 has incompatible enable structure." for TRELLIS_DPR16X4 mean?
<sensille> or can i somehow find the rules myself?
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<sensille> if (last_en_bit != wr_en[i + cell_port_i*mem_width])
<sensille> doesn't help me, though ;)
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<sensille> at least moving the write back one cycle helped
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