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<ross_s>
Following up on earlier, I had some time to put together a small tool for exploring resource usage based on the output from yosys. All source code is here if anyone is interested: https://github.com/rschlaikjer/yostat
<ross_s>
If anyone knows a good way to detect which cells are 'primitives' from the JSON, that would be good to know - currently I just have a list of ECP5 cells
<whitequark>
you basically have to know it upfront
<whitequark>
but you can approximate it very well by looking for the blackbox attribute
<whitequark>
(it's possible that people will add custom blackboxes but it's rare)
<ross_s>
hmm, yeah that looks like it'll work
<ross_s>
will probably patch that in tomorrow
<az0re>
whitequark: Can you remind me of the exact format of hdlname?
<az0re>
And it's just an attribute for wires, right?
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<whitequark>
az0re: the manual has it; the format is a sequence of public names separated by a single space
<az0re>
I need to think if that can be used instead of source location, and if there is a benefit to doing it that way
<az0re>
There is already an attempted name match
<whitequark>
there's one more aspect, which is that a single logical wire can be composed of multiple wires with the same hdlname but nonoverlapping offset/size
<az0re>
Right
<az0re>
I'm not sure that matters, though, as the matching is done SigBit-by-SigBit
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<acomodi>
Hi all, I have a question on verilog attributes. I was using a ~7 months old yosys version, and, upon using the current master, the LOC constraints on primitives of the verilog design stopped to end up in the generated eblif. Has the way of handling attributes changed in these months?
<Lofty>
"LOC constraints on primitives of the verilog design"?
<acomodi>
(* LOC="SLICEXY" *)
<Lofty>
Perhaps you could try a git bisect
<daveshah>
Also, use ilang to see if the attributes exist at various points in the flow
<daveshah>
in particular, whether they are being dropped at the frontend, during flattening or in the bleif backend
<acomodi>
Ok, I'll check that, thanks
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<acomodi>
The attribute absence issue seem to be related to abc9. For instance, when running synth_xilinx without abc9, the LOC attribute does not get dropped, while when enabling abc9, the attribute gets dropped.
<acomodi>
Here's a reduced form of the design: https://we.tl/t-2ziEJMdneo. I tested it on the following yosys version: Yosys 0.9+2406 (git sha1 ede4b10d, clang 6.0.0-1ubuntu2 -fPIC -Os). the run.sh script synthesize without abc9, while the run_abc9.sh enables abc.
<daveshah>
Probably what changed is that flops are now being passed through abc9 to some extent, and the various mappings/unmappings end up losing attributes
<daveshah>
This should definitely be fixed though, as constrained FFs are useful for many a reason
<acomodi>
All right, should I open an issue with the failing test and a brief on GH?
<acomodi>
brief explanation*
<daveshah>
Yes please, I haven't followed abc9 developments that closely recently so I'm not the best person to fix it
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<jeanthom>
Hi, I'm running into a "DQS group mismatch" error when trying to compile a DDR3 design (the full error message is "ERROR: DQS group mismatch, port DQSW270 of 'ddrphy.U$$25' in group LDQ41 is driven by DQSBUFM 'ddrphy.U$$26' in group LDQ77"). I was wondering if it's a bug from nextpnr or if it could be something wrong/missing in my HDL code?
<daveshah>
Does the design build in Diamond?
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<daveshah>
Have you compared the message with the DQS groups (in the pinout file)?
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<az0re>
whitequark: if you rename() a wire or cell in a design, does that update the `hdlname` attribute?
<az0re>
Or does that AttrObject retain its original `hdlname` attribute?
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<mwk>
az0re: it's untouched; how would it even work if you wanted to update it?
<az0re>
Right, just making sure
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