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09:39
<
maartenBE >
Hello, when I use the cxxrtl backend on a simple blinky verilog module, the generated header/source does not contain any blinky specific source.
09:39
<
maartenBE >
This is on current master.
09:40
<
tpb >
Title: Running yosys cxxrtl backend on blinky · GitHub (at gist.github.com)
09:42
<
whitequark >
first off, please don't use the `proc; flatten; clean; splitnets -driver; clean -purge` line
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09:43
<
maartenBE >
Ok, removing it does not change behavior.
09:45
<
whitequark >
it does actually for me
09:45
<
whitequark >
but then it works with that line as well
09:45
<
whitequark >
let me see
09:46
<
whitequark >
which exact commit are you using?
09:46
<
whitequark >
and what is your yosys command line?
09:47
<
maartenBE >
commit 70771352
09:47
<
whitequark >
there's no such yosys commit
09:47
<
tpb >
Title: Merge pull request #2159 from MerryMage/cxxrtl-mul · YosysHQ/yosys@334ec5f · GitHub (at github.com)
09:48
<
maartenBE >
Excuse me, it was 334ec5fa0a9. I accidentally copied the sha256 hash of the zip
09:49
<
whitequark >
how are you running yosys?
09:49
<
maartenBE >
yosys script.ys, under `add_custom_command` inside cmake
09:50
<
whitequark >
if you download your own gist, then run `yosys proc.ys`, does it work for you?
09:51
<
tpb >
Title: debian Pastezone (at paste.debian.net)
09:58
<
maartenBE >
(this is taking long because I just started rebuilding yosys)
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<
maartenBE >
No matter what options I give to make, the generated sources remain the same..
10:58
<
maartenBE >
Is there some way to get more verbose output?
11:00
<
daveshah >
Have you tried it without CMake as wq said yet?
11:01
<
maartenBE >
Yes, same result.
11:02
<
daveshah >
And the design is non-empty before cxxrtl per the ilang output?
11:03
<
tpb >
Title: Running yosys cxxrtl backend on blinky · GitHub (at gist.github.com)
11:03
<
maartenBE >
The blinky module is visible in the ilang file
11:07
<
daveshah >
works fine for me, too
11:07
<
daveshah >
you can pass -g to yosys for slightly more verbose output, but I don't know if that helps much here
11:08
<
whitequark >
yeah, no idea what goes wrong
11:09
<
maartenBE >
I haven't run make test yet, I'll try that
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<
daveshah >
Anything unusual about your OS or toolchain?
11:19
<
maartenBE >
The os is fedora 30, using the system gcc compiler. And I use conan, using system packages (no conan packages).
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<
maartenBE >
The tests run fine...
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<
tnt >
ERROR: Mismatch in directionality for cell port $paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.ram_I.WD0: \ram_I.WD0 <= \ram_wdata
18:45
<
tnt >
I mean ram_I.WD0 is an input ... so I'm not sure what this is complaining about :/
18:46
<
tnt >
Is there anyway to get more details/info ?
18:46
<
Lofty >
If it's an input, then doesn't "\ram_I.WD0 <= \ram_wdata" write to an input?
18:46
<
tnt >
Well ram_wdata is a signal in the module that instanciates ram_I.
18:47
<
Lofty >
No, ignore ram_wdata
18:47
<
Lofty >
If ram_I.WD0 is an input, that line writes to an input port
18:47
<
Lofty >
Which is why you get an error
18:47
<
tnt >
But that "line" is nowhere in the source code.
18:48
<
tnt >
That's the message printed by yosys but " \ram_I.WD0 <= \ram_wdata" is nowhere in my code.
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<
thardin >
does yosys support union types?
19:11
<
daveshah >
I think there was some union support added recently
19:12
<
tnt >
Oh ... did yosys just get something that would make signal[35:36]
_not_ being empty ?
19:12
<
thardin >
hmm.. I'm completely green on systemverilog, is there some magic necessary for yosys to parse files as that?
19:13
<
thardin >
.sv maybe
19:13
<
tnt >
-sv argument to read_verilog
19:14
<
Lofty >
If you pass a file with .sv it'll be inferred as SV
19:14
<
tnt >
oh interesting, didn't know that.
19:14
<
daveshah >
only on the command line, not to read_verilog, right?
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19:18
<
daveshah >
yeah I think it was only merged in the last month or so
19:18
<
daveshah >
and I can't vouch for how complete it is
19:19
<
thardin >
I'm on a0cc795e from march 12th
19:19
<
thardin >
don't need unions quite yet, but it's good to know it's being worked on. indispensible for smaller devices like the hx1k I suspect
19:20
<
thardin >
I'm already doing "poor man's unions" by repurposing counters
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<
tpb >
Title: Fix 0-WIDTH wire handling in techmap rules. · Issue #2058 · YosysHQ/yosys · GitHub (at github.com)
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<
tnt >
lambda: seems related indeed.
20:40
<
tpb >
Title: ast: swap range regardless of range_left >= 0 by eddiehung · Pull Request #2027 · YosysHQ/yosys · GitHub (at github.com)
20:42
<
tnt >
yup. the 'RAMB' wrapper for quicklogic needed a couple of (* force_downto *)
20:43
<
tnt >
although ... that didn't actually fix it :/
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