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<thardin>
is it possible to switch reference clock to the pll on the iCE40HX1K? as in starting it on one clock then switching to another?
<thardin>
I'm looking at the possibility of locking it to a 1-100 kHz reference
<thardin>
synthesizes at least
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<thardin>
assuming I get this to work, it would be kind of amazing
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<llee454>
Hi does anyone know of an appropriate channel to post questions about iceprog?
<Lofty>
Here is fine
<Lofty>
Or ##openfpga
<llee454>
Thanks Lofty. I'm running into a problem where when I attempt to run iceprog it stalls indefinitely trying to clear the flash of an icoboard. When I run `sudo iceprog System.bin` I see the following warning: "Extended Device String Length is 0xFF, this is likely a read error. Ignorig...". Then it never progresses past: "erase 64kB sector at
<llee454>
0x000000.."
<llee454>
Any ideas?
<daveshah>
Are the jumpers on your board definitely configured for flash
<daveshah>
?
<daveshah>
Oh hang on icoboard
<daveshah>
They don't use iceprog, you need to use icoprog
<llee454>
Is it possible to use icestorm (or some other open source programmer) to flash an Icoboard through an Icoboard Base?
<daveshah>
there should be a make option to use USB instead
<llee454>
I see.
<llee454>
I found it. Thanks daveshah, Lofty, and tpb.
<Lofty>
tpb's just a bot
<Lofty>
tpb: version
<tpb>
Lofty: The current (running) version of this Supybot is 0.83.4.1. The newest version available online is 0.83.4.1.
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<llee454>
Can anyone tell me where I can find documentation explaining how to read and write to the SRAM devices embedded on an Icoboard from a Verilog file? Also, where I might find the pcb names for the clock signals?
<Lofty>
As an external device, it'll be accessed as top-level module I/O
<llee454>
Ok. I assume that means that I will need to have a set of inputs/outputs for my verilog module and then connect those ports to the device using a PCB file mapping. But, I'm not sure where the PCB names are documented. Nor do I know where the spec describing the SRAM ports are. Do you know where I can find these?
<Lofty>
I don't, unfortunately
<Lofty>
My expertise is on the Cyclone V ecosystem, mostly >.>
<daveshah>
There should be a schematic on the Trenz site
<llee454>
I see. Thanks Lofty.
<daveshah>
and a part number for the SRAM from which you can find a datasheet
<llee454>
Thanks daveshah
<llee454>
Great I think that I found the schematic (https://drive.google.com/file/d/0By-zY9AlHqXIdHFDZ2Q1aG10eVE/view). It appears that the SRAM device is presented on page 4. Am I right to conclude that I can access the A0 port of the memory device by mapping an output port from my verilog module to IO21B in the PCB file?
<daveshah>
Yes although you use the ball name not the pin name in the constraints file
<daveshah>
So N2 not IO21B
<llee454>
How did you determine that n2 = IO21B?
<llee454>
Nevermind I see.
<llee454>
Thanks!!
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