clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<Lofty> daveshah: what's the default state of iCE40 pullups? Wondering because of https://twitter.com/The6P4C/status/1271791013216976897
<daveshah> it's on if they are unused or the pin is not included in the design; off if the pin is included
<daveshah> they are also on if the chip isn't configured
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<cr1901_modern> git rev-list HEAD@{1}..HEAD | wc
<cr1901_modern> Oh my... :o
<cr1901_modern> 1783 1783 73103
<cr1901_modern> (And that was since January!)
<cr1901_modern> I know I'm a bit late to the party, but what is "abc9" and how does it differ from "abc"?
<Lofty> cr1901_modern: two things; ABC9 is box-aware (e.g. memories and flops are things that cannot be mapped by ABC but are important to know about), and it uses a generalised delay model (e.g. input->output path is measured in picoseconds, and varies for paths, which reflects real-life hardware better)
<Lofty> Another important box is carry logic, where ABC9 can prune carry chains it can prove are unneeded
<cr1901_modern> Is it a special input arg to abc or? I don't think I've ever conciously used it
<Lofty> For Yosys flows, you can enable it with -abc9
<tpb> Title: yosys-cookbook/ecp5.md at master · ZirconiumX/yosys-cookbook · GitHub (at github.com)
<Lofty> (and should for ECP5)
<Lofty> (and Xilinx)
<Lofty> (in Intel, I don't give you a choice; you get ABC9 :P)
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