<matthuszagh>
hi. I've read and optimized a set of verilog modules with yosys. I then write the modules back to verilog with `write_verilog` and then attempt to include them in a design that I synthesize with vivado. However, vivado is complaining about the yosys-generated verilog file. Has anyone else experienced anything like this? Is this normal?
<matthuszagh>
If you're wondering why I'm using such a strange procedure (i.e. why not just synthesize the modules from the start with vivado) I'd be happy to provide further context
<matthuszagh>
i can use synth_xilinx before write_verilog and that almost works (though I get another error), but I was hoping for verilog output that doesn't contain xilinx-specific instantiations that I could synthesize and simulate
<matthuszagh>
If I don't use synth_xilinx I get weird errors like "illegal operand for operator ~", where it's referring to `assign _0256_ = ~sel_i;`
<matthuszagh>
seems like a totally valid verilog statement to me, so I'm not sure why it complains
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<Forty-Bot>
daveshah: I think your first suspicion may be correct; this design has a lot of constant 1s to make the carry chains work
<Forty-Bot>
however, that doesn't really explain the difference in adder frequency
<Forty-Bot>
wrt your second concern, I was running icetime with -i, so there should be no difference there
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<whitequark>
matthuszagh: you should minimize the verilog file that causes errors and share it
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<dormito>
I've noticed that nextpnr-ice40's timing estimate (and pass/fail result) can be wildly different from icetime's timing result. Is one more accurate than the other?
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<Forty-Bot>
and I have determined that the reason icetime was giving such different numbers was because it was assuming an lp device
<Forty-Bot>
dormito: I had the same problem yesterday ^
<dormito>
hmm I'm explicitly specifying (to both nextpnr and icetime) an lp8k
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