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<matthuszagh>
Hello. I'm attempting to synthesize a xilinx 7-series design with yosys. However, the synth_xilinx command gives the error "Conflicting initialization values for \i". In the verilog file it complains about, I declare `integer i;` once, and then use it several times for different for loops. Some of these loops initialize `i` with `i=0` and some initialize it with `i=1`. Is this what yosys is complaining about?
<Lofty>
I think you want `genvar i`, not `integer i`
<matthuszagh>
Lofty: ah, ok. I thought genvar was only for generate blocks, is that incorrect?
<Lofty>
In Verilog (2005?) `for` at the top level of a module == `generate for`
<Lofty>
In other words: you already have a generate block
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<matthuszagh>
Oh good to know, thanks. I will try genvar then
<Lofty>
Yosys is generally a bit stricter to the standard than other compilers
<Lofty>
But its error messages are...not the best
<matthuszagh>
Hm now I'm getting "Left hand side of 1st expression of generate for-loop is not a register!"
<matthuszagh>
for
<matthuszagh>
<matthuszagh>
reg signed [INPUT_WIDTH-1:0] shift_reg [0:M-2];
<matthuszagh>
initial for (i=0; i<M-1; i=i+1) shift_reg[i] = {INPUT_WIDTH{1'b0}};
<matthuszagh>
genvar i;
<matthuszagh>
It should be though. I only use `shift_reg` in clocked always blocks
<Lofty>
I checked the standard; yes, it should be `genvar`.
<matthuszagh>
Lofty: thanks for checking that. Mind pointing me to the page?
<matthuszagh>
trying to get better at going straight to the standard for this sort of stuff, but still a bit inefficient at reading it/finding things
<Lofty>
matthuszagh: IEEE 1364-2005 page 183: "The loop index variable shall be declared in a genvar declaration prior to its use in a loop generate scheme."
<Lofty>
Are you using `i` in multiple loops?
<matthuszagh>
terrific, thanks
<matthuszagh>
yes
<Lofty>
No nested loops with `i` as the same variable, right?
<Lofty>
(the standard forbids that)
<matthuszagh>
Correct, they're separate.
<Lofty>
What happens if you run Verilator on your code?
<Lofty>
(as in, `verilator --lint-only -Wall`
<Lofty>
)
<matthuszagh>
good question, lemme try
<matthuszagh>
Genvar not legal in non-generate for (IEEE 1800-2017 27.4)
<matthuszagh>
Suggest move for loop upwards to generate-level scope
<matthuszagh>
initial for (i=0; i<M-1; i=i+1) shift_reg[i] = {INPUT_WIDTH{1'b0}};
<matthuszagh>
then also
<matthuszagh>
Genvar not legal in non-generate for
<Lofty>
Verilator's using a much later standard than Yosys there :P
<matthuszagh>
there's no way to set the standard to 2005 is there?
<Lofty>
verilator --language 1364-2005
<Lofty>
That matches what Yosys (presently) supports
<matthuszagh>
great
<matthuszagh>
ok basically the same errors
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<matthuszagh>
so it sounds like i have to write generate explicitly?
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<Lofty>
Probably; I'll admit to not being a language lawyer
<matthuszagh>
no worries, i'll try that out
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<matthuszagh>
also strangely, the language verilator flag doesn't seem to be doing much for me
<matthuszagh>
it still complains about 1800-2017 issues
<Lofty>
Maybe the error messages are hardcoded there
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<matthuszagh>
I noticed in the yosys manual (2.2.5) it says for loops are supported in always blocks and in generate statements at the module level
<matthuszagh>
this doesn't say anything about initial blocks
<matthuszagh>
also, the arrays and memories section (2.2.6) uses integer rather than genvar for the for-loop index
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<matthuszagh>
Does every memory assignment/initialization for loop need its own `integer`? I get an error for conflicting initialization values unless I do this.
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