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<rqou> whee, giant SB201 thread on one of the eecs mailing lists
<rqou> dis gun be good
<rqou> fortunately(?) doesn't affect me
<rqou> also, apparently i don't know how to meme and it's supposed to be "dis gon b gud" :P
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<rqou> offtopic: arrgh i have to use numpy again
<rqou> i hate numpy
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<pie_> how hard is a vga controller? i highly doubt im actualy going to but i was wondering about fixing the presumably shorted bitline in my monitor
<pie_> not worth the effort obv ÉP
<pie_> * :P
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<sn00n> hi
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<pie_> death by sn00n sn00n
<sn00n> krkr
<sn00n> futurama right?
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<qu1j0t3> close
<pie_> *vga controller = vga decoder
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<pie_> "What the fuck you climb into the technique if the repair is not in the tooth with your foot in your mouth.
<pie_> Sho fucking on the vylazilo"
<pie_> thanks google translate!
<pie_> " Pipets spring fuck. "
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<sn00n> hum
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<pointfree> I've been thinking about how and why the PSoC 5LP logic fabric is addressed in a checker/xor pattern and is possibly reed-muller logic. Possibly the flexibility of the routing comes from the commutativity and associativity of XOR.
<pointfree> I wrote up a configuration with all routes open to port 2 (0xFF everywhere)
<pointfree> I'm able to invert port 2 (0xAA --> 0x55 and so on)
<pointfree> ...that brings me part of the way to confirming the hypothesis about it using reed-muller logic. Yay!
<awygle> Do FPGAs get cheaper over time? Will a low-end Kintex still be $100+ in five years?
<balrog> pointfree: that is really neat
<awygle> Err this is openfpga whoops. Oh well.
<qu1j0t3> awygle: Yeah. but you may have a lot of trouble running the supporting tooling...
<qu1j0t3> awygle: that rots, while the hardware stays intact...
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<awygle> qu1j0t3: sure, don't want to be the Spartan-6. I'm more interested in long term BOM cost prediction
<awygle> Can always freeze a VM for tooling
<qu1j0t3> ohhhh.
<qu1j0t3> good question. ignore me
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