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<pcbhdl-github> [pcbhdl] whitequark pushed 1 new commit to master: https://github.com/pcbhdl/pcbhdl/commit/08d8ffa29645e5bea2b8a51c9a47cd0ec6215f8c
<pcbhdl-github> pcbhdl/master 08d8ffa whitequark: Experimental automatic component name inference.
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<pie_> one of my friends just started poking at psoc (in a normal sense) is all the psoc reversing work the dudes do up somewhere?
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<balrog> that's pointfree's page
<balrog> also the openocd work
<pointfree> pie_, balrog: http://www.psoctools.org/
<balrog> are PSoC4 UDBs different from 5LP?
<pointfree> ( the replacement for the odroid server )
<pointfree> balrog: Haven't looked into them much but I think so.
<pointfree> The PSoC 4 and PSoC 5LP were designed by different teams, I've heard.
<pointfree> documentation looks somewhat different. That's as far as I've looked into it.
<pointfree> PSoC 4 smartio is interesting. The Cypress analog co-processor has it too.
<pie_> ah ok thanks
<pie_> i think he said he has psoc3
<pie_> ah nothing on that i guess
<pointfree> psoc3 is closer to psoc5lp.
<pointfree> ...and probably has the same UDB's and routing for the most part
<pointfree> although the mappings from DSI to peripherals/gpios will be different at least
<pointfree> I'm writing up a script to automate RE of dsi-to-peripheral interfacing by way of Mill's Methods
<pie_> wowo some crazy tables you guys have
<pointfree> That should correct any errors I might have made for the PSoC 5LP dsi port interface mappings and speed up the process of adding support for PSoC6 and PSoC3
<pie_> whats the reason for the fancy mazelike nature of the switching bits and regs table
<pointfree> The diagonal arrangements of switches can connect to anything in that row or column. The routes do not need to be aligned.
<pie_> this mills method stuff? http://philosophy.hku.hk/think/sci/mill.php
<pointfree> Yea
<pie_> sounds like a rather veiled way of doing logic
<Lord_Nightmare> cr1901_modern and rqou : yeah VRC7 has an instrument ROM using implant ROM on the die; it is not easily extractable via decap, requires delayer and stain
<pointfree> pie_: I guess it's kind of similar to Jean-Francois Nguyen's methods here: https://lse.epita.fr/lse-summer-week-2016/slides/lse-summer-week-2016-07-maxv_cpld.pdf
<Lord_Nightmare> kevtris did audio? a/b tests to figure the rom largely out about 15 years ago. in 2011ish, rainwarrior on nesdev forums did his best at improving it via a/b and waveform comparison, and someone came in the past week or so and posted corrections to that of a few bits
<Lord_Nightmare> its likely about 98%+ correct now
<pointfree> The flexibility of PSoC routing made/makes it difficult to verify which registers are mapped to which switches.
<pointfree> It was throwing me off for a while.
<pie_> pointfree, dumb idea, could you somehow tag specific tihngs by their functionality? somehow forcefully imposing structure?
<pie_> i mean like, if you have an unlebeled graph, with say 4 nodes
<pie_> and theres n edges between the nodes
<pie_> you have no way to tell which is which
<pie_> but if you draw edges between the nodes appropriately you can get a graph which uniquely identifies each node (or at least a few, idk, asspull example)
<pie_> so maybe one node has 1 edge, another has 2 another 3, another 4, then you know which node is which by the structure of the graph
<pie_> of course i dunno how you could use this for deducing things in a binary format x3
<pie_> pointfree, those slides seem neat, this sounds like fun, i should read up on it sometime
<pointfree> I've been using wired logic in the routing fabric to see what's blocked by what. Also, just enable all routes in routing blocks not under consideration. The signal will take whatever path through those routing blocks and routes can be individually enabled in blocks that need to be isolated for RE.
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<pointfree> pie_: I like your idea. Could this be useful for tagging non-GPIO peripherals?
<pie_> i have no ideaaa~~~
<pie_> xP
<pie_> i mean its basically whatever you can come up with so that you can deduce hidden structure
<pie_> i dont really know much about how this stuff works so idk if it even makes any sense. simpler inferences like the slides you linked are probably better? (i only skimmed so i didnt really concretely get what they said)
<pie_> pointfree, i feel like this might be a well defined computer science problem though
<pie_> idk which but it definitely sounds like one imo :D
<pointfree> I also want to get to the bottom of why this flexibility exists. I was reading about reed-muller logic https://www.eetimes.com/author.asp?doc_id=1274545 and then noticed that UDB-A UDB-B checker pattern looks like the reed-muller xor pattern.
<pointfree> Then I started looking at the register addresses in binary and saw reed-muller/xor-xnor logic patterns there too. XOR is associative and commutative so that would account for the flexibility.
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<pie_> hm
<pie_> *shrug* thats your merit, ive no idea :)
<pointfree> I hear reed-muller logic makes testing for stuck-at faults easy http://mark.bu.edu/papers/99.pdf
<pie_> no die photos right/
<pie_> ?
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<pointfree> pie_: none yet. I'm interested to see what a UDB looks like inside. The UDB's are twice the height of an HC block (the largest routing block). That makes the UDB array square and therefore have the largest area. I interested to know how much of the routing structure was copy-pasted for the UDB's.
<pie_> whats a udb
<pie_> wait how do you know how big they are without any photos?
<pointfree> A pld might have that diagonal of switches http://www.fpgacentral.com/pld-types/pla-programmable-logic-arrays ( the OR-array in the pictures linked remind me of the HV column to the side of the large HC block)
<pointfree> pie_: UDB's contain two PLD's, datapath, dynamic configuration ram, status & control blocks, clocking & reset. They are the "logic blocks" between the HC switching matrices.
<pie_> ah
<pointfree> pie_: It's just a calculation with the assumption that the UDB array would be square to maximize area.
<pointfree> digshadow: I was preparing a talk for the Nov 8th mvre but now it looks like there are a few too many unexplained mysteries to be resolved first.
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<digshadow> pointfree: k
<pie_> cr1901_modern, how do i play yu-no
<pie_> :P
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<cr1901_modern> pie_: That's an interesting question to ask me in ##openfpga. But since ##openfpga is a channel dedicated to anime, I guess VNs count
<cr1901_modern> pie_: Download this: http://japanesepccompendium.blogspot.com/2013/07/elf-classics-yu-no-shangrlia-shangrlia.html, mount it using a virtual CD-ROM program (I use WinCDEmu),
<cr1901_modern> then download the translation patch installer on this page and follow the prompts: https://tlwiki.org/index.php?title=YU-NO_-_The_Girl_that_Chants_Love_at_the_Edge_of_the_World
<cr1901_modern> Should just work (I hope)
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<pie_> cr1901_modern, ah i managed to get it working meanwhile
<pie_> took a bit of work for various reasons...
<cr1901_modern> Lol yes as does most Japanese media from that era
<cr1901_modern> Why'd you bring it up/how'd you know I play it? Not sure I ever mentioned it in here
<pie_> it was more a matter of ifguring out wtf was up with encodings, turns out i got it right at one point, just didnt have the fonts :/
<pie_> cr1901_modern, strangely enough i was reading your twitter because of that series of random facts posts
<cr1901_modern> Ahh yes I did post the intro scene/music a few nights ago
<pie_> apparently cheesy vn dialogue is what my life has been missing all this time :P
<cr1901_modern> pie_: It's worth it for the end. I can't really describe it. It's something that has to be experienced.
<pie_> i think ill make it :P
<cr1901_modern> pie_: If it ever annoys you, I would recommend consulting a spoiler-free guide to get past the "adventure game" parts, b/c the final route is the mind blowing part.
<pie_> yeah i think i found one by accident
<pie_> also, uh...crap VNs always give you a bunch of bad endings first?
<pie_> thats doesnt sound good :(
<cr1901_modern> pie_: Some bad ends are unavoidable the first time, indeed
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<azonenberg> pointfree: You do know we have low-res optical photos of a psoc4 UDB right?
<azonenberg> not sufficient to answer detailed questions about logic connectivity, but enough to see the basic floorplan, physical aspect ratio, etc
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<pointfree> azonenberg: Yeah. I guess there could be other blocks outside of the UDB array making the chip square, but it's making the most sense for it to be square from an addressing perspective.
<pointfree> From the addressing, it's looking like the UDB should actually be the height of a single HC. Maybe the system bus is another 96 wires high. http://www.psoctools.org/switching-bits-and-regs.html <-- Looking at the structure of the duplicated-HC-as-UDB, the OR plane column would give enough switching to cover the Input Terms feeding in from the HC. ( need to half the height of the UDB there)
<pointfree> PLD0 and PLD1 would have to be interleaved, but that makes sense because that's how they are addressed.
<pointfree> Then, recall odd vertical HC lines are for the upper UDB and even vertical HC lines are for the lower UDB. So what going on in the UDB's for those columns? Well, the DSI Port Interface has some inverting or XOR logic so I don't know why the UDB Port Interface wouldn't do the same. That takes care of truth + complement.
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