01:56 <azonenberg_work> ZipCPU: wire foo = 42;

01:56 <azonenberg_work> is an assign

01:56 <azonenberg_work> logic foo = 42; is an initial

01:56 <azonenberg_work> that's pretty clear, no?

01:56 <ZipCPU> The spec wasn't that clear

01:57 <azonenberg_work> well, initials for synthesis arent even specified

01:57 <azonenberg_work> they're a widely supported FPGA extension but not technically standard afaik

01:57 <azonenberg_work> i dont think there is a sv fpga synthesis standard

02:00 <azonenberg_work> ZipCPU: more to the point

02:00 <azonenberg_work> (at least in my coding standard)

02:00 <azonenberg_work> it is illegal to have an always_comb and an initial in the same net

02:00 <azonenberg_work> an always_ff and initial can be combined

02:01 <ZipCPU> That I'll agree with

06:53 <swetland> TIL yosys and verilator have very, very different ideas about what "logic" implies in various situations. I just fixed my "runs in sim and not on the metal" issue with s/logic/reg/g ...

12:37 <tnt> I have a ECP3 versa dev kit (new, in box, never used ...) to give away if anyone is interested. Ping me at 246tnt at gmail.

14:12 <gruetzkopf> tnt: you should have mail