Interestingly in process_carries there is a small snippet of code that's commented ... and when I uncomment it, that seems to fix that issue and it now processed the entire chain at once and that bumps my f_max by 10% ...
Arf, but for another design it decreased it by 10% so that might just be random.
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gain cells are neat
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gain cells ?
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daveshah: Looking forward to the opt pass stuff :) Seems to work for me at least.
I will look at the carry pass through stuff. It could be that there is a bug in there
Yosys can generate some strange constructs too
AFAICT it doesn't consider the last LC to be "in the chain" because it has no "carry out".
I think there will be a few more changes to the other chain stuff to make that work for all cases
I know I commented that out for a reason
Separately, the way we do carry pass through should also be improveable
yeah, I figured, but I couldn't firgure out why :p I had hoped you'd remember :p
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It's amazing how easy it is to notice (as a human) that a placement is "weird" ... but how to translate that into code that doesn't produce those placement is ... tricky.
like ... 16 bit register, all bits have the same control set, all inputs come from another 16b reg, no logic. And it's spread across like 8 tiles.
It's quite possibly not suprising in that case
If the outputs fan out to more than one signal in different places than the output then it will probably pull the placement stronger than the input
A single reg to reg path will have a lot of budget too
output go to an adder so not sure about that. But it's no where in the critical path, so the placer just probably didn't care and has no reason to "make it look pretty :p". I was just browsing the placement with the floorplan tool.
tnt: isn't all of p&r basically an AI problem, trying to approximate what a human would do with enough time? :P
[whitequark/Glasgow] whitequark pushed 1 commit to master [+3/-0/±0] https://git.io/fp6vk
[whitequark/Glasgow] whitequark 31fd5ce - arch.boneless: new architecture (Boneless v2).