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<RaYmAn>
whitequark: do you have a "golden sample" firmware hex? I think something is going wrong with my self-built. I haven't succeeded in flashing the eeprom with glasgow after it broke, but I just tried with fx2tool and it wrote the eeprom just fine (with the glasgow hex. I suspect if I write the config too, it'd actually boot)
<tnt>
Glasgow uses slave-fifo synchronous mode right ?
<RaYmAn>
whitequark: bingo, used the one you posted for miek yesterday. Now it flashes oO
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<whitequark>
tnt: yes
<whitequark>
RaYmAn: which sdcc version?
<RaYmAn>
my original version when it sort of worked was Ubuntu version (3.6 I think). latest I admit I built with 3.8 which I guess isn't supported
<RaYmAn>
it's just really bizarre it mostly worked except apparently flashing
<RaYmAn>
thinks were behaving so weird I went WTF I guess.
<whitequark>
RaYmAn: 3.8 is definitely suported
<whitequark>
*supported
<whitequark>
I build with 3.8
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<RaYmAn>
then I'm Lost
<RaYmAn>
I took the ihex you posted and everything instantly worked
<whitequark>
hmmm
<whitequark>
interesting
<whitequark>
how did flashing break?
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<RaYmAn>
after verifying with fx2tool, it claimed to have flashed, verification failed, but literally nothing was written
<whitequark>
hm
<whitequark>
which python-libusb version do you have?
<RaYmAn>
I saw the discussion from yesterday and installed latest from pip
<whitequark>
ok
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<whitequark>
weird.
<RaYmAn>
quite
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<tnt>
whitequark: after carefully looking at the timings for both the ice and the fx2 ... I think the only option is to capture data from the fx2 on the falling edge.
<whitequark>
tnt: yeah, i tried that, actually
<whitequark>
but it broke really badly
<whitequark>
probably because of no SB_GB_IO
<whitequark>
tnt: can you please write your findings down in the issue?
<tnt>
This is the output timings: https://i.imgur.com/JMSbv2P.png so that works fine the FX2 capture window is right into the ice_out data valid window.
<whitequark>
ouch, transparent background
<whitequark>
tnt: so, i'm doing something else right now and don't have the context ready
<whitequark>
think you could put it on github or anywhere at all
<whitequark>
?
<tnt>
Yeah, I'll fill it out in the issue.
<whitequark>
thanks!
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<_whitenotifier>
[Glasgow] smunaut commented on issue #89: Use SB_GB_IO instead of SB_IO+SB_GB - https://git.io/fpM60
<whitequark>
tnt: this is extremely helpful
<whitequark>
and moreover this explains the weird behavor I'm observing with SB_GB_IO
<tnt>
tx. Yeah external interfacing is always tricky in fpga because ... delays everywhere :p
<whitequark>
yeah
<tnt>
will you be at ccc btw ?
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<whitequark>
tnt: i don't know unfortunately
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<tnt>
So .. the CDONE pin is a global clock input .... very useful. But the SPI_SCK pin isn't. Seriously ?
<whitequark>
lol
<daveshah>
tnt: which ice40 is this?
<tnt>
up5k. But that was actually uwg30 package.
<daveshah>
oh, I wonder how that works
<daveshah>
CDONE is a dedicated pin on the sg48
<daveshah>
do they physically tie it together with another pin as part of the WLCSP packaging...
<tnt>
Yeah no idea. And how do you use it ?
<tnt>
like how do you select between cdone and user function ?
<daveshah>
CDONE is open drain
<daveshah>
so it is pulled low during config and then released as tristate aftwards
<tnt>
Oh ... right.
<daveshah>
this makes it of questionable value as an input though
<tnt>
yeah ... maybe a global reset input.
<whitequark>
yep
<whitequark>
i actually should make it a global reset on glasgow
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<tnt>
Do relative constraint work on 'reg' ? i.e. without having to instanciate primitives, I'd like to tell it that (1) those 8 registers need to be in 1 slice and (2) they need to be right next those other 8 registers ?
<daveshah>
If it's nextpnr you are talking about
<daveshah>
Yosys should hopefully keep these attributes
<daveshah>
But nextpnr doesn't have any attribute for relative constraints yet
<whitequark>
yosys might have them on the wrong entity
<whitequark>
wire instead of reg
<whitequark>
we had to tackle that for gp4par
<tnt>
daveshah: oh, I thought nextpnr had relative constraints ...
<daveshah>
It does
* tnt
is confused
<daveshah>
It just doesn't expose them externally yet
<tnt>
Oh ok.
<daveshah>
If nothing else because they are a bit tricky to describe generically
<tnt>
I'm wondering if I can easily generate attributes value in a 'generate' look. (i.e. construct the string from a genvar)
<tnt>
(going back to just instanciating DFFs )
<daveshah>
I'm pretty sure last I looked at something like this I ended up just writing a Python script
<daveshah>
To generate the Verilog
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<tnt>
yeah ... all I find on the internet doesn't seem to work with yosys. When doing things like "0" + i the attribute is no longer a string but becomes an integer / binary string.
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