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<azonenberg>
tnt: yeah its not bad as a file viewer
<azonenberg>
but that's almost never what i want to do :p
<tnt>
:)
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<kbeckmann>
Is there a way to see how much BRAM is used in nextpnr-ec5? I'm probably just not seeing the print.. Or are they somehow incorporated within TRELLIS_SLICE?
<sorear>
Distributed RAM is in slices
<kbeckmann>
Ah, thanks. Sorry for the noise. So I guess I want to make sure DP16KD are used. Was just a bit of a cryptic name :).
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<sorear>
extremely happy that mithro has taken a position in favor of self-contained documentation for FPGA architectures
<sorear>
bad idea: nextpnr gui, but using a micrograph/vectorized "masks" of the actual layout instead of representing arcs and bels with straight lines and boxes
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<azonenberg>
sorear: i actually wanted to do that for coolrunner to some extent
<azonenberg>
it would be stylized a little bit but floorplan-identical to the real chip
<azonenberg>
but like, i'd show stylized gates and muxes instead of physical polygons
<sorear>
(the visual6502 people managed to get an original ARM1 mask set instead of spending time on a decap/delayer and manual cleanup; maybe someone could work connections on project4064)
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<swetland>
azonenberg: vivado does that and it's halfway decent. It definitely seems like you could provide a svg (or whatever) "shape" for LCs, though ideally it'd draw differently depending on the specific config bits of that specific LC
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* swetland
is very much looking forward to a future with 7-series support in a foss toolchain.
<swetland>
I really like the architecture. Pity it's BGA-only and a bit spendy (though spartan-7 helps a bit bringing in lower end parts), but otherwise very enjoyable hw to work with
<azonenberg>
swetland: yeah i know vivado/planahead does
<azonenberg>
except i wanted that for CPLDs :P
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