<TD-Linux>
seems verilator doesn't support mixing blocking and nonblocking on different signals in the same struct
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<zkms>
i need to learn what systemverilog is some day...
<emily>
it's some terrifying blend of verilog and a verification suite i think?
<emily>
XgF/gay in [other channels we share] would know more than me
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<sorear>
i think it's historically like a c/c++ thing, but verilog isn't developed anymore, so it's imo Not Wrong to say that verilog was renamed systemverilog in 2012
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<_whitenotifier>
[whitequark/Glasgow] whitequark pushed 1 commit to master [+0/-1/±1] https://git.io/fpVvO
<TD-Linux>
I have the ucode struct ripped apart now
<TD-Linux>
it's really ugly ;_;
<Bob_Dole>
oh does yosys support system-verilog now?
<TD-Linux>
no
<TD-Linux>
which is why I'm de-system-veriloging this code
<TD-Linux>
it passes around a multiple-hundred-member struct everywhere so it's not pretty
<TD-Linux>
I'm currently just trying to make it work in the verilator subset of sv. yosys will be harder
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<cr1901_modern>
JT12 core should already be in Verilog
<Flea86>
It is, in 2001 form
<Flea86>
There may be a verilog-ised version by the author now, I've not looked lately
<cr1901_modern>
I made a sample SoC to drive the JT51 core https://github.com/cr1901/ymsoc, but I very much doubt it works without changes right now
<Flea86>
My verilog skills still need work, admittedly.. I only know VHDL well.
<Flea86>
Currently in the process of (trying to) finish off the porting of the Genesis core to my Ohm board.
<Flea86>
Everything except JT12 works
<cr1901_modern>
I got JT51 to work on my SoC, but I never managed to get it to sound good (not that I can create FM instruments to save my life in the first place)
<Flea86>
cr1901_modern: I see (and heh me neither..). I'll keep chipping away at it.
<azonenberg_work>
TD-Linux: are you sure implementing sv struct support in yosys isnt gonna be easier?
<azonenberg_work>
(and does verilator do sv?)
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<tnt>
whitequark: did you give a try to the yosys patch wrt CE ?
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<daveshah>
whitequark: merged both PRs
<daveshah>
I'm not sure how best to determine the optimal CE threshold, tbh
<daveshah>
15 seems sensible for now and won't introduce any congestion issues that you might get if it is too high
<TD-Linux>
azonenberg_work, well I also have to make multiple assignment types to a struct in verilator work
<TD-Linux>
azonenberg_work, but yeah it might be. maybe it can be my first yosys patch :)
<TD-Linux>
though, in this case I could just split the huge struct into 2 structs, and avoid that problem in verilator
<azonenberg_work>
i use structs heavily in my vivado sv code
<azonenberg_work>
because interfaces arent fully supported
<azonenberg_work>
in particular vivado cannot do vectors of interfaces
<azonenberg_work>
Which is a pain for any kind of router/switch type ip
<azonenberg_work>
or arrays of cpus
<azonenberg_work>
etc
<azonenberg_work>
so what i do is i split my buses up into an inbound and outbound struct
<azonenberg_work>
and have two struts for every "interface" :p
<azonenberg_work>
it's dirty but it works in vivado
<azonenberg_work>
I want to get yosys to the point i can at least do that
<azonenberg_work>
including combinatorial assignments, =, and <= to different fields of one struct
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<azonenberg_work>
TD-Linux: ^
<TD-Linux>
yeah, it would be a huge improvement if I could just get verilator compatible structs in
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<whitequark>
daveshah: thank
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<f003brv>
Hello
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<pie_>
if i want to pull multiple input pins on a demux (?: i mean many to one) to ground, can i run them all through the same resistor?
<jn__>
pie_: would that imply directly connecting the different signals to each other?
<qu1j0t3>
^
<qu1j0t3>
pie_: in short "no"
<pie_>
but it should be fine because inputs with nothing on them, and not outputs?
<pie_>
i mean, thats my reasoning at least
<qu1j0t3>
you aren't using the inputs? then yes it's ok
<qu1j0t3>
if you still wanted independent inputs then the pulldowns would have to be independent, but i guess that's obvious already?
<q3k>
i just keep flushing out of my memory what the current state is
<q3k>
anyway, i'm trying to synthesize f32c via verific/vhdl
<q3k>
and they have a instantiation of their register file for ice40 using SB_RAM256x16
<q3k>
but they also have a generic one, will try that and see if yosys infers that into bram
<q3k>
but i should just write a wrapper and add it into yosys :/
<q3k>
SB_RAM40_4K 8
<q3k>
SB_RAM40_4KNR 64
<q3k>
it did infer it though :)
<daveshah>
Yosys definitely beats the ice40 tools at inferring bram
<q3k>
too bad it won't fit in an hx8k :P
<q3k>
i'll reduce the bram
<q3k>
as in the ram of the core
<q3k>
yeah, i'm surprised how good that inference is at times
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<pie_>
does it make a difference if i place the resistor between the flip flop and the first optocoupler (7-1 pins), or before ground? https://a.uguu.se/AZBsRw1msPpD.png
<pie_>
i feel like putting it before ground might isolate it better from other parts of the circuit or something but idk if that makes any sense
<pie_>
on the other hand, i guess the flip flip would be sourcing current from vcc more or less directly so thats kind of the same thing but the other way around?
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<tnt>
pie_: not really no.
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<_whitenotifier>
[whitequark/Glasgow] whitequark pushed 2 commits to master [+1/-0/±1] https://git.io/fpwaX
<_whitenotifier>
[whitequark/Glasgow] whitequark c39afbf - support.pyrepl: do not crash if _ is not defined.
<whitequark>
pie_: depnds on how the flip flop output cascade is implemented
<whitequark>
is it CMOS? TTL?
<tnt>
what would that change ? I mean anything high voltage enough to break the opto isolation would fry both cmos and ttl no matter where the resistor is ...
<whitequark>
tnt: no i mean, just for making sure the circuit works in the first place
<tnt>
Ah yeah that :)
<tnt>
1.5V Vf per led ...
<tnt>
OTOH they make photo "relays" rather than this dual opto connection.
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<_whitenotifier>
[Glasgow] whitequark opened issue #83: Applet analyzer does not work with async applets - https://git.io/fpwo0
<_whitenotifier>
[Glasgow] whitequark commented on issue #62: Use USB type C connector - https://git.io/fpwoV
<_whitenotifier>
[Glasgow] whitequark opened issue #84: ATECC508A - https://git.io/fpwo6
<_whitenotifier>
[Glasgow] whitequark edited issue #6: IC footprints - https://git.io/fpwoP
<_whitenotifier>
[Glasgow] whitequark opened issue #85: TCA9517 - https://git.io/fpwKf
<_whitenotifier>
[Glasgow] whitequark edited issue #6: IC footprints - https://git.io/fpwoP
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