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<tnt>
Mmm, afaict arachne's failing initial placement of my design because it just fills the LC randomly at the beginning and at some point it runs out of tiles with CE / SR
<tnt>
and I guess next-pnr fails for the same reason since AFAICT the initial placement also doesn't have any "smarts" in it.
<daveshah>
nextpnr should rip up in this case
<tnt>
I'm trying to work my way through understanding how place_initial() works atm.
<tnt>
Is there a document explaining the nomenclature of nextpnr ? Bel / Cell / ... ?
<tnt>
So in ice40, a cell would be a single LUT+FF+Carry right ? not the entire tile of 8 of those ?
<daveshah>
yes, at the point of placement
<daveshah>
before packing, cells can also be single LUTs, FFs, etc
<daveshah>
the packer combines those into the LUT+FF+Carry `ICESTORM_LC` which are placed
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<tnt>
AFAICT it only ripsup the Bel that are "isValidBelForCell". But here, to find some space, it should rip up some other ones an combine them to free up entire tiles.
<daveshah>
yes, that could probably be improved
<tnt>
Ok, being a bit smarter and packing compatible cells initially if possible, it gets a bit further. 272 cells placed vs 212 initially. Still not enough though :/
<tnt>
I see the --pack-only option, but is there a ways to export the design "as packed" so I can look exactly wtf it came up with ?
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<tnt>
Oh come on it just doesn't like me I think ... 338 cells placed of 354.
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<tnt>
Looking at the synthesizer output, I think yosys is a bit generous in sprinkling clock-enables ... sometimes it's better to just take the old input and mux old vs new than using register CE. Especially in the ice40 where the cost of using CE for a single FF is pretty high.
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<tnt>
Wait ... on the ice40, is the Reset also gated by CE ?
<tnt>
oh yeah, it is. I didn't expect that. Always thought reset overwrote CE.
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<daveshah>
tnt: have you seen the "-nodffe" option
<daveshah>
this is a bit of a known issue
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<tnt>
daveshah: Ah, no I hadn't seen that. Doesn't help though :/ There are a bunch of places where the enable is useful for wide buses and with -nodffe the design is now 383 LC ... out of 384, doesn't fit either :/
<tnt>
Ideally I'd like such option only if the CE is used for 1 or 2 FFs only.
<tnt>
this is the distribution of net-name, and # of times that net is used as a CE.
<daveshah>
it should be possible to create such an option
<tnt>
I'm wondering is this is something yosys should do, or done in next-pnr 'pack' ?
<sorear>
this all seems like very blunt instruments
<daveshah>
something yosys should do
<daveshah>
that way you can do logic optimisation afterwards still if needed, etc
<daveshah>
I'm also not sure if best to not infer these enables in the first place, or blast them out later
<sorear>
I'm guessing "intelligently decide *which* CEs to use" is "ideas for future theses" territory
<daveshah>
definitely
<daveshah>
it's certainly not something I have time for in the forseable future
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<tnt>
Yeah, the "intelligently" part sure isn't trivial ... but at least in the ice40 the cost of a CE used a single time is pretty high :/
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<SolraBizna>
What would it take to add SB_RGBA_DRV support to nextpnr myself?
<daveshah>
Two things - the bitstream stuff and making sure you don't add SB_IOs to the RGB pins
<daveshah>
The bitstream stuff could just be copied from arachne
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<SolraBizna>
alright... I'm gonna give it a shot
<Bob_Dole>
there's dedicated rgb pins on the ice40s?
<tnt>
Bob_Dole: yes
<SolraBizna>
on the UltraPlus at least
<tnt>
Bob_Dole: with programmable constant current drivers.
<SolraBizna>
and nextpnr is currently configuring mine to be eye-meltingly bright white by default :D
<tnt>
SolraBizna: huh you manage to instanciate the block at all ? When I try, it assert()
<SolraBizna>
it doesn't instantiate, I had to `ifdef` out my RGBA LED code
<SolraBizna>
but meanwhile, those bits of CRAM are getting set to 0 (I guess) and ... bye bye retinas
<whitequark>
ahaha do you have the UP5K devboard
<SolraBizna>
UPDuino v2.0
<whitequark>
oh
<whitequark>
the UP5K devboard has a LED you can see from low earth orbit, too
<whitequark>
where do they even get the cursed things
<daveshah>
istr at school the teacher taping over the RGB LED on a microcontroller devboard because he thought it was so bright it was a safety hazard
<daveshah>
probably true too
<SolraBizna>
I have to configure it for 2mA current (out of 48 maximum o_O) and PWM it at about 1/4 duty cycle before it is bearable
<SolraBizna>
I think I've added the relevant bitstream stuff and prevented it from wanting to add SB_IOs... now I've got to the "no timing info for port" part
<daveshah>
Just return TMG_IGNORE
<daveshah>
Timing is kind of irrelevant for this cell anyway
<SolraBizna>
I was hoping it might be that easy
<tnt>
whitequark: hehe, yeah, I need to set it to lower current + half current + only pwm it at like 1/8 duty cycle not to be blinded :)
<SolraBizna>
Fatal error: file not found 6
<SolraBizna>
...cute
<SolraBizna>
the message seems to be coming from an attempt to execute a file with the exact path of "6"
<tnt>
Meh .. determining how many time a CE line is used in yosys seems ... hard. I thought I'd do an "unmap" pass after the dff2dffe pass is done, but it seems at that point all the CE wires are "different" somehow, no idea how to determine they are in fact the same wire.
<daveshah>
I don't know Yosys obscurities too well
<daveshah>
But maybe opt_clean after dff2dffe might help
<daveshah>
Otherwise I think you'll have to get in touch with clifford
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<SolraBizna>
trying it with a simpler design gets "ERROR: No wire found for port RGB1 on source cell RGB_DRIVER." (or RGB2 or RGB0, at random) and I'm stumped
<SolraBizna>
(it makes it through place, though)
<daveshah>
Ah you need to trim the connections from those pins
<daveshah>
Because they are top level pins, they don't have an internal wire associated with them in the database as there's nowhere to route to
<SolraBizna>
I thought I had, but now I'm not so sure
<SolraBizna>
pack_io in pack.cc looks like the right place to be doing this
<tnt>
daveshah: running opt_merge does a bunch of things like https://pastebin.com/EzvtdUqN which seems good. However grabbing the getPort from DFFE, I still see the original name, I'm not sure how to determine it;s connected somewhere.
<daveshah>
SolraBizna: yes, pack_io is definitely the right place
<daveshah>
tnt: this is beyond my Yosys knowledge at this point
<tnt>
SolraBizna: I once at a look at adding support as well and what I started to do was basically grep everywhere things like SPRAM or MAC appeared in the code to see how those were special cased around the codebase. Not sure if that helps.
<tnt>
daveshah: ok, thanks.
<SolraBizna>
Same here, and that got me this far
<tnt>
What's the best way to contact clifford ? Open an issue on github ? Mail ?
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<whitequark>
github
<daveshah>
yeah
<tnt>
tx
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<tnt>
Arf, finally came up with an initial placement algo that fits ... only to have the simulated annealing rip it up and not come up with another valid placement.
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<SolraBizna>
heh
<tnt>
SolraBizna: how is your rgb doing ?
<SolraBizna>
I'm stuck trying to trim the connections
<SolraBizna>
I'm not sure how to generalize the code that's already here
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<SolraBizna>
I'm pretty sure I got everything else though
<tnt>
\o/ I found how to make yosys do what I want. And then next-pnr can also place the design. And then fails with "ERROR: Assert `src_wire != WireId()' failed in /tmp/ice40/nextpnr/common/router1.cc:869.".
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<tnt>
Ah well, apparently if you have an inout wire that's not connected in your top level, it triggers that asserts.