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<SolraBizna>
why does it creep me out when a tool successfully identifies and global-promotes my clocks
<daveshah>
heh, global clock promotion is one of the easiest parts of the flow tbh
<SolraBizna>
I imagine so
<SolraBizna>
the thing that *should* be creeping me out is the BRAM promotion that's happening
<SolraBizna>
AFAIK, there's no logic in here that should be promotable, but... the tools do not lie
<SolraBizna>
s/promotion/inferrance/
<daveshah>
Yosys is pretty clever at BRAM, as long as it is possible within the limits of the hardware
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<GuzTech>
Hi \o
<GuzTech>
Question: I've got to nerdsnipe some potential embedded systems master student, and I want to show a cool FPGA demo. What would you consider?
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<IanMalcolm>
are small patches that only fix compiler warnings accepted on nextpnr?
<daveshah>
yes, definitely
<IanMalcolm>
cool, let me get a PR ready then
<daveshah>
thanks!
<IanMalcolm>
done (:
<IanMalcolm>
I was trying to get the gui to run on my system (I'm getting a segfault, probably due to some cursedness of homebrew/pyenv python), and I ran into a few compiler warnings
<IanMalcolm>
I'm sure the issue is with my system, but I'm trying to get nextpnr to fail gracefully when it meets with this case
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<behzatc>
Hi all! Is there any 'speed grade' type maximum frequency benchmark that compares ICE40 UP / LP / HX series posted anywhere?
<SolraBizna>
The LP+HX datasheet gives a few timing numbers for very simple primitives