<tnt> daveshah: ok. Completely unrelated : How does cascade works ? In http://www.clifford.at/icestorm/logic_tile.html I don't see any bit that controls it ?
<whitequark> it's always connected
<tnt> Huh ? AFAIK it replaces in_2 of the lut above ... so it can't be always enabled ?
<whitequark> mm, sec
<whitequark> right, there's a mux
<q3k> mithro: say, did you ever implement rescaling for timvideos/hdmi2usb?
<q3k> s,rescaling,scaling,
<mithro> q3k: Not yet, we have the primitives required to do color accurate combination of pixels
<mithro> tnt: I have a diagram of it somewhere
<q3k> mithro: i'm mostly interested in upscaling (720p to 1080p)
<mithro> q3k: That is pretty easy
<q3k> i mean, i guess nearest neighbour works here
<q3k> not sure
<mithro> tnt: Which of course I can't find now...
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<tnt> mithro: lol
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<SolraBizna> protip: store critical variables in ROM to save on RAM :D
<SolraBizna> (I'm really cross with myself for taking nearly two days to figure out that was what I was doing wrong)
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<s_frit> nice new guide to setting up ICE40 open source tools: https://www.youtube.com/watch?v=dTL0qrzme4g "Getting started with the Lattice iCE40 FPGA: Programming w/ Open Source Tools"
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<_whitenotifier> [whitequark/Glasgow] whitequark pushed 2 commits to master [+0/-0/±3] https://git.io/fpWdW
<_whitenotifier> [whitequark/Glasgow] whitequark 8136c16 - applet.jtag.mec16xx: implement "functional" firmware read and write.
<_whitenotifier> [whitequark/Glasgow] whitequark af45db5 - applet.jtag.{mec16xx,xc9500}: fix typo.
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<_whitenotifier> [Glasgow] Error. The Travis CI build could not complete due to an error - https://travis-ci.org/whitequark/Glasgow/builds/457361082?utm_source=github_status&utm_medium=notification
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<sensille> anyone interested in an old ALL-03 universal programmer?
<gruetzkopf> Hmm. Which insert?
<gruetzkopf> I have a ALL-something programmer but only a PLCC64 insert
<sensille> right on top
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<_whitenotifier> [whitequark/libfx2] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/fplFS
<_whitenotifier> [whitequark/libfx2] whitequark fcedc47 - Fix typo.
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<_whitenotifier> [whitequark/Glasgow] whitequark pushed 3 commits to master [+0/-0/±4] https://git.io/fplN8
<_whitenotifier> [whitequark/Glasgow] whitequark 1c06aa2 - setup: fix typo.
<_whitenotifier> [whitequark/Glasgow] whitequark 5e4d193 - applet.spi.{master,flash_25c}: add missing @synthesis_test.
<_whitenotifier> [whitequark/Glasgow] whitequark 4190b20 - support.endpoint: cancel recv() on end-of-stream.
<mwk> who the fuck designed the abomination that is xilinx tile coordinate system
<mwk> or rather multiple abominations, because why would there be only one
<whitequark> xilinx
<mwk> I mean, for fuck's sake
<mwk> I got most of the rules more or less correct for spartan6 already
<mwk> but there are some tiles that just have random _X<x>Y<y> suffix completely unrelated to the place they are located, particularly around the transceivers
<mwk> and I'm half-wondering if whatever tool they used to generate the chip description tiles just read uninitialized memory and stuffed it there
<whitequark> dart board
<whitequark> with a die shot glued to it
<_whitenotifier> [whitequark/Glasgow] whitequark pushed 3 commits to master [+0/-0/±4] https://git.io/fplhI
<_whitenotifier> [whitequark/Glasgow] whitequark 2f0fe95 - applet.jtag.pinout: fix test_build().
<_whitenotifier> [whitequark/Glasgow] whitequark 4fcd0b7 - applet.spi.flash_avr: fix build().
<_whitenotifier> [whitequark/Glasgow] whitequark cb4b8d3 - access.simulation.multiplexer: implement FIFO flush, as a stub.
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<_whitenotifier> [whitequark/Glasgow] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/fp8f5
<_whitenotifier> [whitequark/Glasgow] whitequark 337de22 - applet.spi.flash_avr: add missing @simulation_test.
<_whitenotifier> [whitequark/Glasgow] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/fp8Je
<_whitenotifier> [whitequark/Glasgow] whitequark 328aba5 - applet.spi.flash_avr: add missing @synthesis_test.
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<tnt> "Info: promoting $PACKER_VCC_NET [logic]"
<tnt> Yeah, totally the best use of a global buffer.
<whitequark> lmao
<whitequark> i mean if it's used for nothing else
<whitequark> it could relieve routing congestion
<whitequark> vcc_net has a really high fanout
<tnt> I'd actually be curious to see where it's really used. I mean as far as I understand the icestorm docs, most of the cells have 'default state' that are driven appropriately if not driven by something else.
<whitequark> yes, and it's 0
<whitequark> you have to explicitly use a LUT to make an 1
<tnt> Not all of them. Things like CE have default 1'b1 I think.
<whitequark> sure
<tnt> I'm not sure if nextpnr knows that if I connected .CE to 1 in my code, there is no need to actually route VCC there.
<daveshah> CE is a special case that should be correctly dealt with
<daveshah> LUT inputs at constant 1 could be dealt with by changing the LUT table but I don't think this is in nextpnr
<tnt> daveshah: sorry , missed it :/ https://github.com/YosysHQ/nextpnr/pull/135
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<Bob_Dole> SolraBizna's been having trouble with the arduino as a means of talking to his upduino after programming it, so does anyone know if the usb-spi ftdi chip on it can be used for 2-way communication with the programmed core?
<SolraBizna> it's an FT232H
<Bob_Dole> s/upduino/upduino v2/
<SolraBizna> it's wired for programming the configuration flash, but that does mean three of its pins are connected to pins on the iCE40 that can be used as IOs
<SolraBizna> (not counting the EEPROM chip-select, which I don't want to touch for obvious reasons)
<tnt> Bob_Dole: yes, I'm doing it ...
<tnt> _but_ you need to either use SRAM programming, or disconnect the flash cs after boot.
<tnt> (or using another line for chip select)
<cr1901_modern> What's "CE" in this context?
<SolraBizna> Clock Enable
<SolraBizna> so, the flash is programmed by putting the FT232H into MPSSE mode and manually banging on the flash CS and CRESET lines
<SolraBizna> if I put the FT232H into UART mode, the flash CS becomes DTR# (an output), and the CRESET becomes RI# (an input)
<SolraBizna> which isn't usable because the board doesn't pull CRESET
<SolraBizna> so I guess I get to invent some MPSSE-based protocol
<tnt> well ... I was using SPI
<SolraBizna> the designer of the UPDuino helpfully failed to hook CDONE up to anything but an LED
<whitequark> why do you even use an UPduino...
<tnt> you can have sevral cs line in the ftdi, so why not stick with SPI protocol ?
<Bob_Dole> cheap, available, specifically noted on the risc-v contest.
<SolraBizna> because I'm poor as heck
<SolraBizna> I couldn't even afford an UPDuino, Bob_Dole bought me one the day before the contest runners announced free ones
<whitequark> well ok, the risc-v contest runners made an awful decision
<whitequark> upduino is a horrible board
<SolraBizna> tnt: if I were designing the board, this would all be so very moot
<tnt> that's why we have AWG30 wires :p
<whitequark> that doesn't unfuck the updiono PLL
<SolraBizna> nothing can unfuck the UPDuino PLL
<tnt> No, I meant for the spi chip select ...
<whitequark> ah
<SolraBizna> I'm just going to do something SPI-like without touching the MPSSE GPIO lines
<sorear> not the only questionable decision there
<tnt> I got USB core from tinyfpga runnin on a upduino and using the PLL just fine :P Just added "a few" decoupling caps and better grounding wires.
<SolraBizna> tnt: I don't have soldering capability either
<cr1901_modern> is upduino that "scenic route ground trace" board?
<whitequark> yes
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<daveshah> The version 2 does at least have a ground plane
<daveshah> Although strangely they went for 1 ground and 1 Vcc plane on a 2 layer board
<daveshah> And it's so dense the plane is pretty split
<daveshah> Making it still pretty crap
<cr1901_modern> use a pour if you insist on 2-layer boards?
<cr1901_modern> /me looks at his two layer boards and hides them behind a curtain
<daveshah> The sensible thing would have been 2 ground planes and a Vcc trace imo
<cr1901_modern> tnt: I'm a bit muddled atm. I'll close that issue in a bit once I can test. Or better yet, you can close and if anything goes wrong I'll let you know :)?
<cr1901_modern> err s/muddled/in a fog/
<sorear> how can you have 2 entire planes + other traces on a 2 layer board?