<azonenberg_work>
also interesting, xilinx bought neocad in 1995
<azonenberg_work>
so was lattice using neocad before that?
<azonenberg_work>
then xilinx stopped selling them licenses?
<gruetzkopf>
LB->PCI, PCI->PCIE, PCIE->TBT
<gruetzkopf>
you could also talk pci directly
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<cr1901_modern>
daveshah: Not that this is an invalid approach (far from it :P), but why do you opt to create your own primitives for ECP5 rather than use the Lattice names?
<cr1901_modern>
Even doing "tinyprog -a 1179648 -p morse.bit" results in this error
<cr1901_modern>
tinyfpga: Overriding the prompt with the following command line results in a user bitstream which doesn't boot- after a second or so, it goes back to the bootloader
<cr1901_modern>
s/following/above/
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<cr1901_modern>
awygle: While it's on my mind... I had to create a Migen platform in-place for testing: http://ix.io/1qSe This is how you do it without needing to make a PR to add it to a centralized repo :).
<cr1901_modern>
Not that it'll make you feel better about Python
<awygle>
cr1901_modern: thanks
<awygle>
:-)
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<daveshah>
cr1901_modern: because the Lattice primitives have cryptic names, and I wanted one flipflop primitive with parameters as that was easier to work with than loads of different ones
<daveshah>
You could add a tehhmap to Yosys to convert the Lattice to Trellis ones easily enough
<daveshah>
azonenberg_work: I think Xilinx bought NeoCAD later than that? Anyway, before then NeoCAD were in a bad financial state and sold a general license to ATT/Lucent who became Lattice
<azonenberg_work>
then lattice forked it when xilinx bought them?
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<daveshah>
azonenberg_work: Yup
<daveshah>
The codebases obviously diverged but they still both use ncd files
<azonenberg_work>
can they parse each others files? :p
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<daveshah>
No, they encrypt them differently
<azonenberg_work>
ncd files are encrypted?
<daveshah>
Pretty sure one of the vendors are anyway
<azonenberg_work>
huh
<daveshah>
They both have tools to go to a text format anyway
<daveshah>
XDL or NCL
<azonenberg_work>
yeah i know, thats why i was thinking encrypting the ncd was ludicrous :p
<azonenberg_work>
also, did neocad sell licenses to anyone else?
<daveshah>
Well, those tools won't work, at least for Lattice, if the is licensed ip in the design
<azonenberg_work>
i'm thinking more like a generic ncd parsing libary
<azonenberg_work>
and wait, so lattice wont let you export a ncl of an ip core?>
<azonenberg_work>
interesting
<daveshah>
I don't think so
<daveshah>
Not the paid for IP anyway
<azonenberg_work>
i havent tried doing an xdl/edif export of secureip
<Bob_Dole>
how much slower are the UP5ks vs LP and/or HX variants? Asking because I just bought a board with one for SolraBizna
<azonenberg_work>
daveshah: so according to that thread, neocad routed better than xilinx's internal tool did lol
<daveshah>
azonenberg_work: yup
<azonenberg_work>
i can only imagine how bad their old router must have been
<azonenberg_work>
if a distant ancestor of the ISE router outperformed it :p
<cr1901_modern>
How much high quality routing can be done in 640kB?
<daveshah>
Bob_Dole: up5k LUT delay is about twice that of the lp8k (so about half the the speed)
<Bob_Dole>
for some reason, that's what I thought I remembered it being. Thank you
<azonenberg_work>
daveshah: i did work with the xc4000 series on a dec alpha, circa 2010-2011
<sorear>
SA is time-intensive, not memory-intensive; the state you need for SA is basically just the bitstream, and there are representation tricks where you can work directly on a somewhat compressed version
<azonenberg_work>
(yay for schools using decades-old tech lol)
<azonenberg_work>
but i wasn't pushing performance
<sorear>
i could pnr for a hx8k with less memory than an uncompressed bitstream, i'm pretty sure
<azonenberg_work>
we were doing an ide hdd controller :p
<daveshah>
I found an ATT brochure with all the specs circa 95
<daveshah>
Needed 16MB of RAM in 1995 on PC or 32MB on UNIX
<daveshah>
Seems like quite a bit for the time
<daveshah>
The tiny gui screenshot in the page before is a tool still included in Diamond, and still called EPIC
<daveshah>
Although I think someone ported it from motif from qt, the same buttons are even in the same places
<azonenberg_work>
daveshah: lol, motif
<azonenberg_work>
brings back memories of fpga_editor
<daveshah>
I spent some time the other day compiling 32 bit motif to get microsemi's tools to work
<sorear>
> The combinatorial propagation delay through the network is independent of the logic function generated and is spike-free for single-input variable changes.
<sorear>
that's an unexpected claim. glitch-free LUTs in the ATT3000
<daveshah>
Not surprised, in the dark ages when dinosaurs roamed the earth and motif was a good gui toolkit, people would have been doing all sorts of horrible async stuff
<daveshah>
It is nice they give a basic LUT delay in the datasheet. That has also gone out of fashion
<sorear>
…internal tristates/wired-AND on pg 14
<daveshah>
Crystal support is kind of neat, all current FPGAs need an oscillator
<daveshah>
I wonder if that is something that will return on very low cost parts
<daveshah>
More accurate than internal, cheaper than an external oscillator
<azonenberg_work>
i cant remember the last time i used a crystal for anything
<azonenberg_work>
a lot of my boards these days use mems oscillators instead of quartz
<azonenberg_work>
and those that don't, use quartz oscillators
<cr1901_modern>
quartz != crystal?
<sorear>
surprised that as late as 1997 SPI wasn't standard
<sorear>
7.0V absolute maximum Vcc, fancy
<azonenberg_work>
cr1901_modern: quartz crystal vs quartz oscillator
<azonenberg_work>
vs mems oscillator (mems resonant elements by themselves don't seem to be a thing)
<azonenberg_work>
cr1901_modern: i mean sure, quartz oscillators contain a crystal and load caps internally, but you dont care about the details
<azonenberg_work>
it's just voltage in, square/sine wave out
<cr1901_modern>
cr1901cc -pedantic-errors
<azonenberg_work>
side note, i would love to see a decap of a quartz oscillator
<azonenberg_work>
the driver chip and resonant element side by side would probably look cool
<azonenberg_work>
And i'm legitimately curious what the driver asic would look like
<azonenberg_work>
reading analog vlsi is not my expertise :)
<daveshah>
I cut the top off one of the larger dip ones once and the IC was in a sot-23-6 package on a ceramic type substrate with the quartz in the middle
<daveshah>
Was just an off the shelf oscillator ic
<daveshah>
Obviously the small SMD ones will just have a chip in them
<cr1901_modern>
A package inside a package?
<daveshah>
Yup
<sorear>
do any MEMS oscillators have "Maximum He vol%" in their datasheet operational conditions section
<daveshah>
lol
<daveshah>
"Please contact SiTime in case you are planning to use a SiTime device in large concentrations of small-molecule gas, so that we can recommend an appropriate, immune part."
<mithro>
The (yet unfinished rewrite) has *significantly* reduced the resource usage and moved most of the stuff into user mode - https://github.com/tinyfpga/tinyusb
<daveshah>
Perfect
<daveshah>
I hope it also works reliably on the UltraPlus after the rewrite
<daveshah>
If it isn't already
<mithro>
daveshah: All the low level parts are apparently working well on the iCE40UP5K
<mithro>
Just for everyone's information -- I have no financial stake in the project. Just been donating funds + resources to get it to happen.
<daveshah>
Awesome, this will mean all the icevision boards I have might finally be useful too
<wbraun>
cool. Thanks for the link!
<mithro>
daveshah: Yeah, should make the icebreaker itsy viable
<wbraun>
So it does not yet work on the iCE40UP5K but it should?
<daveshah>
Yes
<mithro>
wbraun: The old TinyFPGA-Bootloader doesn't work on the iCE40UP5K
<daveshah>
The strange thing is on the vendor tools it can meet timing by a scrape but still not work
* mithro
works on trying to get the repo for the hardware up for everyone to look at
<daveshah>
The UltraPlus IO are quite slow too I think
<wbraun>
I was playing with the ice storm tools and the iCE40UP5K and it seems a lot slower than the performance optimized iCE40 parts.
<daveshah>
Yes, it's much slower
<wbraun>
the example picorv SOC fails timing at 12MHz...
<daveshah>
About half a LP
<mithro>
Wish I had enough time to get it all up before :-)
<daveshah>
tbh if power isn't a concern the ecp5 is a much better buy
<daveshah>
The 12F is in the same price bracket and over 6 times faster
<mithro>
daveshah: The ECP5 doesn't come in a WCSP 2.5mm x 2.5mm if I understand correctly? :-P
<wbraun>
its annoying that the ecp5 parts are only 0.8mm BGA
<daveshah>
mithro: sure
<wbraun>
0.8mm BGA requires smaller space / trace than most of the cheap board houses / oshpark
<daveshah>
But how many applications were power isn't a concern as qualified above actually *need* that small size