<azonenberg_work> lol
<gruetzkopf> i can tape one to TB
<gruetzkopf> only takes like 3 bridge ICs
lovepon has quit [Ping timeout: 260 seconds]
<azonenberg_work> gruetzkopf: tb-usb, usb-jtag?
<azonenberg_work> :p
<azonenberg_work> also interesting, xilinx bought neocad in 1995
<azonenberg_work> so was lattice using neocad before that?
<azonenberg_work> then xilinx stopped selling them licenses?
<gruetzkopf> LB->PCI, PCI->PCIE, PCIE->TBT
<gruetzkopf> you could also talk pci directly
Bob_Dole has quit [Ping timeout: 252 seconds]
Bob_Dole has joined ##openfpga
Miyu has quit [Ping timeout: 268 seconds]
_whitelogger has joined ##openfpga
sgstair has quit [Disconnected by services]
ym has joined ##openfpga
unixb0y has quit [Ping timeout: 244 seconds]
sgstair has joined ##openfpga
unixb0y has joined ##openfpga
GenTooMan has quit [Quit: Leaving]
specing has quit [Remote host closed the connection]
<cr1901_modern> daveshah: Not that this is an invalid approach (far from it :P), but why do you opt to create your own primitives for ECP5 rather than use the Lattice names?
<cr1901_modern> tinyfpga: I can confirm this behavior (minus the bricking): https://github.com/tinyfpga/TinyFPGA-Bootloader/issues/27
<cr1901_modern> http://ix.io/1qRW
<cr1901_modern> Even doing "tinyprog -a 1179648 -p morse.bit" results in this error
<cr1901_modern> tinyfpga: Overriding the prompt with the following command line results in a user bitstream which doesn't boot- after a second or so, it goes back to the bootloader
<cr1901_modern> s/following/above/
Bike has quit [Quit: Lost terminal]
<cr1901_modern> awygle: While it's on my mind... I had to create a Migen platform in-place for testing: http://ix.io/1qSe This is how you do it without needing to make a PR to add it to a centralized repo :).
<cr1901_modern> Not that it'll make you feel better about Python
<awygle> cr1901_modern: thanks
<awygle> :-)
Miyu has joined ##openfpga
maciejjo has quit [Ping timeout: 260 seconds]
maciejjo has joined ##openfpga
hackkitten has quit [Ping timeout: 260 seconds]
rohitksingh has joined ##openfpga
m_t has joined ##openfpga
lovepon has joined ##openfpga
_whitelogger has joined ##openfpga
lovepon has quit [Ping timeout: 250 seconds]
dingbat has quit [Quit: Connection closed for inactivity]
wbraun has quit [Quit: wbraun]
<daveshah> cr1901_modern: because the Lattice primitives have cryptic names, and I wanted one flipflop primitive with parameters as that was easier to work with than loads of different ones
<daveshah> You could add a tehhmap to Yosys to convert the Lattice to Trellis ones easily enough
<daveshah> azonenberg_work: I think Xilinx bought NeoCAD later than that? Anyway, before then NeoCAD were in a bad financial state and sold a general license to ATT/Lucent who became Lattice
<azonenberg_work> then lattice forked it when xilinx bought them?
rohitksingh has quit [Ping timeout: 268 seconds]
<daveshah> azonenberg_work: Yup
<daveshah> The codebases obviously diverged but they still both use ncd files
<azonenberg_work> can they parse each others files? :p
m_t has quit [Remote host closed the connection]
<daveshah> No, they encrypt them differently
<azonenberg_work> ncd files are encrypted?
<daveshah> Pretty sure one of the vendors are anyway
<azonenberg_work> huh
<daveshah> They both have tools to go to a text format anyway
<daveshah> XDL or NCL
<azonenberg_work> yeah i know, thats why i was thinking encrypting the ncd was ludicrous :p
<azonenberg_work> also, did neocad sell licenses to anyone else?
<daveshah> Well, those tools won't work, at least for Lattice, if the is licensed ip in the design
<azonenberg_work> i'm thinking more like a generic ncd parsing libary
<azonenberg_work> and wait, so lattice wont let you export a ncl of an ip core?>
<azonenberg_work> interesting
<daveshah> I don't think so
<daveshah> Not the paid for IP anyway
<azonenberg_work> i havent tried doing an xdl/edif export of secureip
<daveshah> Seems Motorola used neocad too
<daveshah> https://groups.google.com/forum/m/#!topic/comp.arch.fpga/DDwLWc-hyyg
<Bob_Dole> how much slower are the UP5ks vs LP and/or HX variants? Asking because I just bought a board with one for SolraBizna
<azonenberg_work> daveshah: so according to that thread, neocad routed better than xilinx's internal tool did lol
<daveshah> azonenberg_work: yup
<azonenberg_work> i can only imagine how bad their old router must have been
<azonenberg_work> if a distant ancestor of the ISE router outperformed it :p
<cr1901_modern> How much high quality routing can be done in 640kB?
<daveshah> Bob_Dole: up5k LUT delay is about twice that of the lp8k (so about half the the speed)
<Bob_Dole> for some reason, that's what I thought I remembered it being. Thank you
<azonenberg_work> daveshah: i did work with the xc4000 series on a dec alpha, circa 2010-2011
<sorear> SA is time-intensive, not memory-intensive; the state you need for SA is basically just the bitstream, and there are representation tricks where you can work directly on a somewhat compressed version
<azonenberg_work> (yay for schools using decades-old tech lol)
<azonenberg_work> but i wasn't pushing performance
<sorear> i could pnr for a hx8k with less memory than an uncompressed bitstream, i'm pretty sure
<azonenberg_work> we were doing an ide hdd controller :p
<daveshah> I found an ATT brochure with all the specs circa 95
<sorear> i have zero idea what the memory requirements of an analytic placer are
<daveshah> Ah, this one is better
<daveshah> p28
<daveshah> Needed 16MB of RAM in 1995 on PC or 32MB on UNIX
<daveshah> Seems like quite a bit for the time
<daveshah> The tiny gui screenshot in the page before is a tool still included in Diamond, and still called EPIC
<daveshah> Although I think someone ported it from motif from qt, the same buttons are even in the same places
<azonenberg_work> daveshah: lol, motif
<azonenberg_work> brings back memories of fpga_editor
<daveshah> I spent some time the other day compiling 32 bit motif to get microsemi's tools to work
<sorear> > The combinatorial propagation delay through the network is independent of the logic function generated and is spike-free for single-input variable changes.
<sorear> that's an unexpected claim. glitch-free LUTs in the ATT3000
<daveshah> Not surprised, in the dark ages when dinosaurs roamed the earth and motif was a good gui toolkit, people would have been doing all sorts of horrible async stuff
<daveshah> It is nice they give a basic LUT delay in the datasheet. That has also gone out of fashion
<sorear> …internal tristates/wired-AND on pg 14
<daveshah> Crystal support is kind of neat, all current FPGAs need an oscillator
<daveshah> I wonder if that is something that will return on very low cost parts
<daveshah> More accurate than internal, cheaper than an external oscillator
<azonenberg_work> i cant remember the last time i used a crystal for anything
<azonenberg_work> a lot of my boards these days use mems oscillators instead of quartz
<azonenberg_work> and those that don't, use quartz oscillators
<cr1901_modern> quartz != crystal?
<sorear> surprised that as late as 1997 SPI wasn't standard
<sorear> 7.0V absolute maximum Vcc, fancy
<azonenberg_work> cr1901_modern: quartz crystal vs quartz oscillator
<azonenberg_work> vs mems oscillator (mems resonant elements by themselves don't seem to be a thing)
<azonenberg_work> cr1901_modern: i mean sure, quartz oscillators contain a crystal and load caps internally, but you dont care about the details
<azonenberg_work> it's just voltage in, square/sine wave out
<cr1901_modern> cr1901cc -pedantic-errors
<azonenberg_work> side note, i would love to see a decap of a quartz oscillator
<azonenberg_work> the driver chip and resonant element side by side would probably look cool
<azonenberg_work> And i'm legitimately curious what the driver asic would look like
<azonenberg_work> reading analog vlsi is not my expertise :)
<daveshah> I cut the top off one of the larger dip ones once and the IC was in a sot-23-6 package on a ceramic type substrate with the quartz in the middle
<daveshah> Was just an off the shelf oscillator ic
<daveshah> Obviously the small SMD ones will just have a chip in them
<cr1901_modern> A package inside a package?
<daveshah> Yup
<sorear> do any MEMS oscillators have "Maximum He vol%" in their datasheet operational conditions section
<daveshah> lol
<daveshah> "Please contact SiTime in case you are planning to use a SiTime device in large concentrations of small-molecule gas, so that we can recommend an appropriate, immune part."
<sorear> if you sell me a chip that doesn't work in a He environment and don't disclose this fact, i'm gonna be pissed
<azonenberg_work> s/chip/phone/ ?
<sorear> as a hypothetical corporate buyer of chips I would have more leverage than as an individual buyer of phones
<azonenberg_work> true
<qu1j0t3> lol, yes slightly
<azonenberg_work> i was thinking an institutional device buyer
<azonenberg_work> like a gov agency etc
<azonenberg_work> or hospital
<azonenberg_work> :p
Moiman has left ##openfpga [##openfpga]
<sorear> didn't occur to me that the hospital might *not* be byod
<azonenberg_work> this one was. but in general not always
<qu1j0t3> plus there must be MEMS oscillators in a fair amoutn of other hospital gear?
<daveshah> I do suspect the iPhone one was particularly sensitive
* qu1j0t3 nods
Bike has joined ##openfpga
Laksen has joined ##openfpga
specing has joined ##openfpga
rohitksingh has joined ##openfpga
rohitksingh has quit [Ping timeout: 252 seconds]
Miyu is now known as hackkitten
rohitksingh has joined ##openfpga
Maya-sama has joined ##openfpga
Maya-sama is now known as Miyu
Laksen has quit [Quit: Leaving]
dingbat has joined ##openfpga
rohitksingh has quit [Ping timeout: 250 seconds]
mumptai has joined ##openfpga
wbraun has joined ##openfpga
lovepon has joined ##openfpga
Bob_Dole has quit [Remote host closed the connection]
s_frit has quit [Remote host closed the connection]
s_frit has joined ##openfpga
mumptai has quit [Remote host closed the connection]
azonenberg_work has quit [Ping timeout: 268 seconds]
futarisIRCcloud has joined ##openfpga
<mithro> My new Fomu (Tomu FPGA) board is "officially" announced! - HackADay Presentation @ https://j.mp/tomu-had18 - CrowdSupply Campaign at https://j.mp/fomu-cs
azonenberg_work has joined ##openfpga
<whitequark> nice
<wbraun> As far as I know, none of the iCE40 chips have native USB connectivity. How does the USB connectivity work? Is there some second processor?
<wbraun> Or is there a really small FPGA USB stack I don’t know about?
<whitequark> there is
<wbraun> link?
<wbraun> they don’t mention it on any of the slides and I would be surprised if it did not a comparable number of LUTs as a RISC-V core.
<daveshah> It is pretty large
<daveshah> istr a couple of thousand
<daveshah> Might make more sense to do some at least part software USB stack in user mode
<mithro> The (yet unfinished rewrite) has *significantly* reduced the resource usage and moved most of the stuff into user mode - https://github.com/tinyfpga/tinyusb
<daveshah> Perfect
<daveshah> I hope it also works reliably on the UltraPlus after the rewrite
<daveshah> If it isn't already
<mithro> daveshah: All the low level parts are apparently working well on the iCE40UP5K
<mithro> Just for everyone's information -- I have no financial stake in the project. Just been donating funds + resources to get it to happen.
<daveshah> Awesome, this will mean all the icevision boards I have might finally be useful too
<wbraun> cool. Thanks for the link!
<mithro> daveshah: Yeah, should make the icebreaker itsy viable
<wbraun> So it does not yet work on the iCE40UP5K but it should?
<daveshah> Yes
<mithro> wbraun: The old TinyFPGA-Bootloader doesn't work on the iCE40UP5K
<daveshah> The strange thing is on the vendor tools it can meet timing by a scrape but still not work
* mithro works on trying to get the repo for the hardware up for everyone to look at
<daveshah> The UltraPlus IO are quite slow too I think
<wbraun> I was playing with the ice storm tools and the iCE40UP5K and it seems a lot slower than the performance optimized iCE40 parts.
<daveshah> Yes, it's much slower
<wbraun> the example picorv SOC fails timing at 12MHz...
<daveshah> About half a LP
<mithro> Wish I had enough time to get it all up before :-)
<daveshah> tbh if power isn't a concern the ecp5 is a much better buy
<daveshah> The 12F is in the same price bracket and over 6 times faster
<mithro> daveshah: The ECP5 doesn't come in a WCSP 2.5mm x 2.5mm if I understand correctly? :-P
<wbraun> its annoying that the ecp5 parts are only 0.8mm BGA
<daveshah> mithro: sure
<wbraun> 0.8mm BGA requires smaller space / trace than most of the cheap board houses / oshpark
<daveshah> But how many applications were power isn't a concern as qualified above actually *need* that small size
<tinyfpga> mithro, daveshah: new USB device for new bootloader is here https://github.com/tinyfpga/TinyUSB
<tinyfpga> it has waaaay better timing margin than old bootloader
<tinyfpga> And will be easier to reuse for other applications
<daveshah> tinyfpga: Awesome
<tinyfpga> daveshah: not quite finished yet :(
knielsen has quit [Ping timeout: 246 seconds]
<cr1901_modern> I hope XIP (from flash) can execute insns/copy data fast enough to keep the core happy
<daveshah> cr1901_modern: on the UltraPlus you have enough ram to run all hot paths in ram
<daveshah> Don't even need a cache, just some linker attribute and startup code magic should do the trick
<cr1901_modern> yea but I want to deploy on tinyfpga BX as well
<daveshah> In that case QSPI DDR and compressed instructions are as good as you can get
<daveshah> Still only a max of 8 bits per cycle so half what the core needs
<daveshah> If ram clock is the same as cpu clock