<_whitenotifier>
[Glasgow] kbeckmann opened issue #79: Performance issues when writing lots of data - https://git.io/fp0Ys
<_whitenotifier>
[Glasgow] kbeckmann edited issue #79: Performance issues when writing lots of data - https://git.io/fp0Ys
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<adamgreig>
(cross-asking from #yosys because apparently tnt might have a good idea:) I have an ice40 hx8k design using a pll with a clock into GBIN0 (on the same cell as the X16/Y33 PLL); arachne places fine but nextpnr errors saying the PACKAGEPIN for the SB_PLL40_PAD must be GBIN5 (X16/Y0, the cell with the other PLL)
<adamgreig>
I'm guessing it's picked the other PLL and then complained that the pad input is not in that cell, but I'm not really sure. any ideas?
<cpresser>
I fail to find the power requirement for the ice40up. how much current does my supply need to provide?
<daveshah>
cpresser: It depends on your design. The static power is 75µA. I would be surprised if a design needed a core power of more than 50mA
<cpresser>
i found this one table which says startup peak power = 12mA
<cpresser>
perhaps i should also look into all the appnotes
<cpresser>
but it looks like a 150mA LDO should be enought for the 1v2 core supply
<daveshah>
Power is quite hard to define for an FPGA, because the theoretical worst case design will be a lot higher than any sensible user design
<swetland>
I was bummed to learn it was a 3+ supply device the other day
<daveshah>
Certainly a 150mA LDO is more than enough
<tnt>
I made a up5k design toggling 3000 FFs at every cycle at 87.5 MHz and core power was slightly less than 50 mA.
<swetland>
not the end of the world, but so much else about it is nicely simple
<daveshah>
swetland: you can get away with VccNVCM coming from a diode from 3.3V
<daveshah>
that is what Lattice do in all their app notes
<swetland>
oh cute
<adamgreig>
if you don't need nvcm you can just put 3v3 onto vccnvcm, aiui
<swetland>
then it's just core and io?
<adamgreig>
the abs max is 3v6
<daveshah>
requiring 1.2V core does keep power down too compared to an internal LDO
<swetland>
yeah I doubt I'd ever use OTP vs external spiflash
<cpresser>
the 'reference design' (as in lattice breakout boards) just has a 1.2 and 3.3 supply
<cpresser>
and the diode trick
<adamgreig>
ice40 lp/hx at least, the recommended operating conditions for VPP_2V5 when using spi config are 2.3-3.46V
<adamgreig>
so I think the diode is only required if you plan to actually program the flash
<whitequark>
except they use a schottky
<whitequark>
instead of a silicon diode
<whitequark>
lmao
<daveshah>
:D
<daveshah>
as for VccPLL
<daveshah>
they managed to put the filter cap *before* the 100R resistor
<cpresser>
the example has "CDBU0520" which drops around 0.15V
<cpresser>
daveshah: yep, that was a wtf moment; I moved the caps in my design
<swetland>
hw vendor reference designs are similar to hw vendor driver code... use caution at a minimum
<adamgreig>
throw in the bin and ignore
<swetland>
adamgreig: well sometimes they contain valuable clues about the truth behind the lies in the datasheets
<cpresser>
its usually a good staring point.
<adamgreig>
depends on the vendor i guess
<tnt>
I make a small up5k board for experimentation and in doubt, I had 1.5A supply for Vcore, 2.5v IO and 3.3v IO ... I think that was a bit overkill now :p
<daveshah>
Yes :P
<daveshah>
Maybe if you *really* overvolt
<tnt>
Well ... I originally soldered the fpga 90 deg off because I misread the pin1 marker on the silk screen ... no idea what voltage I sent where.
<tnt>
Still works :p
<qu1j0t3>
wow
<cpresser>
i will most likely have 150mA Vcode and 200mA Vio. should be enough. battery powered, for the lulz
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<mithro>
whitequark: Any idea how long you have to wait after a EOP before you can start a new packet?
<whitequark>
mithro: EOP?
<whitequark>
context?
<mithro>
whitequark: End of Packet (USB high speed)
<whitequark>
ah
<whitequark>
no idea
<whitequark>
I haven't implemented USB on that level
<mithro>
Seems like "7.1.18.1 Low-/Full-Speed Bus Turn-around Time and Inter-packet Delay" -- "A device must provide at least two bit times of inter-packet delay. "
<swetland>
something I'm kinda surprised more FPGA hobbyists don't play with is Ethernet. 10/100 PHYs are $1-3 in qty1 and RMII is surprisingly simple to interface with
<qu1j0t3>
azonenberg_work has simply claimed that ground and won't cede an inch
<qu1j0t3>
all the experimentation
<adamgreig>
swetland: have you done a mac on fpga? i'm actually looking at this today for a little hobby thing
<adamgreig>
torn between a $1 PHY and a $3 MAC+PHY
<adamgreig>
microchip make three different families of MAC+PHY which you can talk to over a SPI or a 16-bit bus and just blat packets at
<adamgreig>
(one they made themselves, one they bought from SMSC, one they bought from micrel)
<adamgreig>
also I'd have expected mii to be easier than rmii to diy on an fpga
<adamgreig>
since you don't have to fuss with clocks so much
<adamgreig>
not sure how much of my {time,ice40hx8k} would be taken up by a mac though
<azonenberg_work>
That's an 8 port SGMII line card
<swetland>
ah
<azonenberg_work>
LATENTRED will be a 24x 1G + 4x 10G port 1U ethernet switch
<azonenberg_work>
three of those line cards, a backplane, and a brain board that has a big beefy kintex-7 for the switch fabric and an INTEGRALSTICK to run the CLI
<azonenberg_work>
the FPGA will be used for I/O expansion because the kintex doesnt have enough pins left after 24 lanes of SGMII and a QDR-II+
<azonenberg_work>
The original plan was to have the stm32 and a spartan7 on that board but i realized the combo was likely to be something i'd use in other projects so i refactored and put it into its own board
<azonenberg_work>
then i swapped the spartan for an artix to get more pins
* swetland
nods
<swetland>
this is a familiar story
<azonenberg_work>
right now i have the line card ready for fab (but may need tweaking of connector placement once i finish the brain board)
<azonenberg_work>
i have to design the backplane and brain still
<azonenberg_work>
integralstick is almost ready for fab
<azonenberg_work>
the 10G MAC/PCS core is ready to go
<azonenberg_work>
the 1G MAC is ready to go but i have to write a GMII-SGMII bridge
<azonenberg_work>
the MAC address table with learning and vlan support is ready to go
<azonenberg_work>
the arbitration and forwarding fabric for the switch needs to be written