<jn__>
why doesn't SF build skyscrapers for housing?
<jn__>
(also: oh, this is ##openfpga, so i guess san francisco's housing problems are slightly off-topic)
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<qu1j0t3>
jn__: ...they... don't? this city sure does
<qu1j0t3>
fwiw
<jn__>
i'm not so sure, but there seem to be huge parts of it covered with two-storey buildings
<jn__>
(ok, i don't actually have much of a clue about this)
<qu1j0t3>
:)
<qu1j0t3>
nah you're right, SF is "special"
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<SolraBizna>
when I was growing up in California and asked my parents why there weren't many skyscrapers around, they said something about the water table being too high
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<sorear>
whitequark: it seems deliberate and relevant here that the ordered sets are multiples of 4 symbols in length
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<whitequark>
hmm
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<whitequark>
daveshah: so I'm thinking
<whitequark>
if I do FSM pipelining, I might need to retire a lot of TLP symbols per clock
<whitequark>
it might make more sense to start with a FIFO-based design and expand it later
<sorear>
i wonder how much it complicates that TLPs/DLLPs are striped across lanes while ordered sets are replicated for each lane
<whitequark>
not very
<whitequark>
but PCIe is a huge spec and I need to start small
<daveshah>
Yeah, the pipelined design could get pretty large
<daveshah>
FIFO seems like a good place to start
<gruetzkopf>
what are you doing between the DLLP layer and the TLP layer? 32bit wide fifos?
<whitequark>
I don't know yet
<whitequark>
right now I'm trying to get TSn FSMs to work after gearbox
<whitequark>
I mean, I'm writing gateware for it.
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<whitequark>
sweet, symbol aligner works
<daveshah>
nice
<whitequark>
now i think i'm going to abstract over width-N *aligned* parsing
<whitequark>
this doesn't need a pipelined FSM
<whitequark>
this needs just a *generalized* FSM
<whitequark>
variable width
<whitequark>
migen is so powerful
<daveshah>
That makes sense
<whitequark>
I cannot conceive writing this in verilog
<daveshah>
I really want to do more with migen at some point
<whitequark>
like, it takes me minutes to write bug-free code *and* tests that would have probably taken days in bare verilog
<whitequark>
if possible at all
<whitequark>
it's absurd
<whitequark>
and migen isn't even a very good abstraction
<zkms>
i want to learn migen now
<whitequark>
:3
<whitequark>
feel free to ask me anything
* zkms
nod
<GuzTech>
I want to try Litex/Migen/Misoc, but I've never managed to install them :'(
<GuzTech>
I'm on Arch so my packages were too new when I tried it like a year ago.
<GuzTech>
Let's see if it works now.
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<GuzTech>
Hmm, I tried it with Conda, but when I try to build something for let's say the Arty board, I get a python error: name 'synth_mode' is not defined
<whitequark>
sounds like you're using litex
<GuzTech>
I'd *like* to use litex
<GuzTech>
If I could get it working that is
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<_whitenotifier>
[whitequark/Yumewatari] whitequark pushed 1 commit to master [+0/-0/±3] https://git.io/fpqDQ
<_whitenotifier>
[whitequark/Yumewatari] whitequark fd7e9b4 - Switch SERDES to 1:2 gearing. This breaks the PHY (for now).
<_whitenotifier>
[whitequark/Yumewatari] whitequark pushed 1 commit to master [+2/-0/±1] https://git.io/fpqyq
<_whitenotifier>
[whitequark/Yumewatari] whitequark 8afe8ea - Implement symbol slip based comma aligner, post-SERDES.
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<_whitenotifier>
[whitequark/Yumewatari] whitequark pushed 2 commits to master [+0/-0/±4] https://git.io/fpq78
<_whitenotifier>
[whitequark/Yumewatari] whitequark c0b6169 - gateware.phy.PCIeRXPHY: simplify, for parser conversion.
<_florent_>
GuzTech: sorry, it's fixed, i broke that while merging between migen <--> litex earlier today
<GuzTech>
_florent_: Ah, cool! I'll check it out
<daveshah>
_florent_: well done on your litedram work!
<_florent_>
daveshah: thanks, but i'm just using your toolchain as a traditional toolchain and it works :)
<daveshah>
:D
<_florent_>
daveshah: it's still without the PLL, i'll test with the PLL soon
<daveshah>
that should be working now
<daveshah>
please do report if you have trouble with it
<GuzTech>
_florent_: It works!
<GuzTech>
Can I also specify on the command line where Vivado is located? Since I haven't installed it in the default location.
<_florent_>
ok i'll do that. i'll also probably do some testing with just the PLL and a scope
<_florent_>
GuzTech: yes, --gateware-toolchain-path should do what you want
<sorear>
litedram on ecp5?
<daveshah>
SDRAM only, atm, of course
<daveshah>
DDR3 next year :P
<GuzTech>
Hmm, it still cannot find vivado
<GuzTech>
Ah nevermind, I had to point it to the directory where 2017.4 was installed.
<sorear>
oh right, litedram is the controller
<GuzTech>
But how would I select which version of Vivado I want if I have more than one version?
<_florent_>
daveshah: i started creating the ddr3phy, i'll try to get that working before the end of the month (with diamond at least)
<daveshah>
awesome
<sorear>
that would work using e.g. DQSDLL primitives?
<_florent_>
sorear: for now i'm using the same approach we used on 7-series and we don't need it
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<_whitenotifier>
[whitequark/Yumewatari] whitequark pushed 1 commit to master [+1/-0/±2] https://git.io/fpmst
<_whitenotifier>
[whitequark/Yumewatari] whitequark a206581 - gateware.phy.PCIeRXPHY: rewrite to use a parser.
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<_whitenotifier>
[whitequark/Yumewatari] whitequark pushed 1 commit to master [+0/-0/±3] https://git.io/fpmui
<_whitenotifier>
[whitequark/Yumewatari] whitequark c2ab023 - gateware.phy.PCIeRXPHY: add support for parsing at 1:n gearing.
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<_whitenotifier>
[whitequark/Yumewatari] whitequark pushed 1 commit to master [+0/-0/±5] https://git.io/fpmaQ
<_whitenotifier>
[whitequark/Yumewatari] whitequark 7c0df16 - gateware.serdes.PCIeSERDESAligner: implement based on SymbolSlip. Also update PHY testbench to use geared PCIeRXPHY. Unfortunately the PCIeTXPHY doesn't do gearing yet.