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<SolraBizna> synchronous and asynchronous memory on the same bus, because why not
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<Ultrasauce> ...bricked my first icestick
<whitequark> how?
<Ultrasauce> not sure. the ft2232 refuses to enumerate
<whitequark> huh
<Ultrasauce> i'll probably check its eeprom tomorrow
* cr1901_modern is reminded he needs a SOIC clip and keeps forgetting to buy one
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<TD-Linux> my friend bricked an icestick but I haven't determined the cause of death yet
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<daveshah> Think I'm close to a ECP5 serdes mvp
<daveshah> the SERDES PLLs are working, I'm getting some kind of output data, it's just not syncing very well
<daveshah> but I don't really have a proper test set up
* daveshah looks for short sma cables
<daveshah> Changed those links to "differential pairs" and it's working!!!1!
<daveshah> that demo is counter -> 8b10 ser -> dodgy wires -> 8b10b deser -> leds
<marshallh> nice
<sorear> Loopback mode would be cheating? :p
<gruetzkopf> very nice
<daveshah> sorear: naturlich
<gruetzkopf> have a free ü
<daveshah> I even set up the compose key
<daveshah> just cba to use it lol
<gruetzkopf> i have compose setup to, but öäüß are native on iso-de keyboards
<felix_> wow, nice! (the open source too support for ecp5 gigabit transceivers, not the wiring ;P )
<gruetzkopf> the wiring is gruetzkopf-approved :P
<daveshah> it's dodgy on purpose to make sure that the equalisation and CDR is working at the limits of its specification :P
<gruetzkopf> too bad the versa has baseT, not SFP
<daveshah> yeah
<daveshah> the baseT connectors are on PHYs with both RGMII on normal pins and SGMII on the SERDESs
<daveshah> if you want to play with that
<gruetzkopf> can you set these phys to the fun rgmii to sgmii mode?
<daveshah> gruetzkopf: yes, looks like it
<gruetzkopf> oh, also supports proper base-x on that interface
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<daveshah> If anyone wants to play with the SERDES stuff, better point out that this needs the following branches of prjtrellis/nextpnr/yosys:
<daveshah> The external reference primitive isn't supported yet, the refclk needs to come from fabric (should be fine for 2.5Gbps but maybe not for 5Gbps), nor is the dedicated clock divider primitive (but I'm not 100% when that is needed)
<daveshah> The example how to use it is here: . Leave the top level serdes pins unconnected and manually constrain the SERDES using the Bel attribute
<daveshah> I'll tidy all this up over the next few days
<gruetzkopf> the more fun clocking modes will be interesting (those with non-identical clock in the same block, lattice has a table of supported combinations somewhere, i'll go hunt for it)
<daveshah> yeap
<daveshah> fun times are ahead
<daveshah> we need a FOSS replacement for the configuration tool in Diamond next
<sorear> how much fun times does SCI entail
<daveshah> shouldn't be too bad
<daveshah> the register space is at least vaguely documented in Lattice's docs
<daveshah> the pins seem relatively intuitive
<daveshah> the "SCAN" pins seem interesting, I'm not sure if this is just for factory test or whether it's some kind of built-in eye test type functionality
<gruetzkopf> built-in eye test is usually well advertised
<daveshah> maybe it's broken
<daveshah> the sim model for the serdes is sadly encrypted
<daveshah> so not a useful source of this info
<sorear> is "foss sim models of everything" at all in scope for trellis?
<daveshah> yes, definitely
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<openfpga-github> [libfx2] whitequark pushed 3 new commits to master:
<openfpga-github> libfx2/master 0613cfe whitequark: Fix DFU ABORT request handling.
<openfpga-github> libfx2/master 8e8db54 whitequark: Don't require a connected device for `fx2tool dfu`.
<openfpga-github> libfx2/master 3a572fa whitequark: Use firmware PID, not firmware PID + 1 for DFU suffix....
<openfpga-github> [libfx2] whitequark pushed 2 new commits to master:
<openfpga-github> libfx2/master c0db272 whitequark: Use small memory model for DFU bootloader....
<openfpga-github> libfx2/master 3c448fd whitequark: Fix another operator precedence issue....
<whitequark> daveshah: wow, that is a LOT of defparams
<daveshah> whitequark: yeah the serdes are a bit crazy
<daveshah> This was all just taken from a core generated by Diamond
<whitequark> hmm okay
<whitequark> guess i'll try to bring it up via diamond first...
<whitequark> are those documented at least?
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<daveshah> No, not really
<whitequark> oh.
<whitequark> that's a pain
<daveshah> They do document the sci registers
<daveshah> Some of them are the same
<whitequark> hmm
<daveshah> In the long term I would like a FOSS replacement config wizard
<azonenberg_work> daveshah: instead of a wizard
<azonenberg_work> i would prefer a parameterized module
<azonenberg_work> where you can go SerdesWrapper #(".INTERFACE("1000BASE-X"))
<azonenberg_work> and it would do the config for you
<azonenberg_work> i have that for 7-series GTPs but 1000base-X is the only one i've pulled out the settings for so far
<whitequark> i agree
<daveshah> Sounds like something that would be nice in migen tbh
<daveshah> Doing pll calculations in pure Verilog seems a pain
<whitequark> ... i will write it i guess if someone tells me how to serdes :p
<gruetzko-> for some interfaces, sure
<whitequark> azonenberg_work: oh so, question
<azonenberg_work> whitequark: answerr
<whitequark> so let's say i receive pcie over the rx pair of the lane
<whitequark> i recover clock from transitions, right?
<whitequark> how does this work exactly? does the serdes integrate with a pll?
<whitequark> afaik refclk is only used for tx
<daveshah> The serdes does also need a reference clock
<whitequark> daveshah: does it have a delay block then?
<daveshah> But it does actual calibration to the received data stream
<azonenberg_work> my understanding is that the pll uses the refclk to get in the approximate range
<azonenberg_work> then locks to the incoming data
<azonenberg_work> but it needs a reference to get close
<daveshah> The ref clock typically needs to be within 100s to 1000s of ppm
<whitequark> daveshah: azonenberg_work: do i understand it correctly that refclk needs to be fairly precisely the same as data clock, but
<whitequark> there need not be any phase relationship
<gruetzko-> yes
<daveshah> Exactly
<whitequark> ok, thought so
<daveshah> Without spread spectrum refclk can be independent
<gruetzko-> well
<daveshah> With SS refclk should probably be shared
<gruetzko-> pcie do IRSS
<whitequark> i'll need to lock onto refclk first, then, before serdes bringup
<gruetzko-> independent-refclk-spread-spectrum
<whitequark> that seems simpler than the bajillion parameter serdes block lol
<gruetzko-> one of the crazier modes
<gruetzko-> you won't see it
<whitequark> gruetzko-: yeah i've heard that pcie "can" work without refclk
<whitequark> but no one actually does it
<whitequark> because it doesnt work in real world
<gruetzko-> without SS it's really common
<whitequark> wait, really?
<gruetzko-> inside specialty devices
<whitequark> ive been told that because of power saving modes or something you ... oh
<gruetzko-> not in actual users machines
<whitequark> yeah if you never go out of L0 that works i think
<gruetzko-> but it's a thing you as the core implementer don't care about
<whitequark> ... where do you know this from, anyway?
<whitequark> why do you have so much cursed pcie knowledge
<gruetzko-> preseeding organic memory over years of scrolling through stuff
<whitequark> mkay
<daveshah> The Versa board has an ispclock for refclk management
<gruetzko-> should have grabbed the versa when it was 100$ a few years back
<whitequark> daveshah: wait, what?
<whitequark> daveshah: are you saying i can't feed refclk into the fpga pll or
<daveshah> we discussed this the other day because it was breaking jtag
<whitequark> that seems unnecessarily complicated
<daveshah> You don't need to use the FPGA PLL at all
<whitequark> what if i *want* to use the FPGA PLL
<whitequark> because i don't want an ispclock on my design
<whitequark> hypothetically
<daveshah> You don't need that either
<daveshah> The serdes has its own PLL too
<gruetzko-> you throw your REFCLK into the serdes
<whitequark> oh.
<whitequark> oh nice
<gruetzko-> one pll per two serdes iirc?
<azonenberg_work> yeah, fpga clock trees have a lot more jitter than the serdes pll
<daveshah> The ispclock is just for routing and a bit of cleaning
<azonenberg_work> this is true in asics too, normally any high speed serial will have a separate dedicated clock input
<whitequark> hmmmm yeah i'll definitely have to build at least the diamond reference design
<daveshah> At the moment nextpnr doesn't support the dedicated path into the serdes pll, only through fabric
<daveshah> This should be fixed tomorrow
<whitequark> to see if this crap even works in my tbt box
<daveshah> Yeah, defo
<daveshah> There's even a bitstream somewhere
<daveshah> The ecp5 serdes do also support the sideband stuff for PCIe
<daveshah> If that's useful
<gruetzko-> iirc even sata sideband is supported
<gruetzko-> *sata inband
<azonenberg_work> gruetzko-: yeah i want to play with that
<azonenberg_work> i've been thinking of building an fpga based 1U "san-in-a-box" gizmo eventually
<azonenberg_work> basically N m.2 sata ssd's on a carrier board
<azonenberg_work> then an fpga bridging it out to iscsi
<azonenberg_work> over 10/40GbE
<whitequark> daveshah: oh a bitstream? hmmm
<whitequark> well i have diamond now anyway
<whitequark> wait
<whitequark> i dont htink i have a diamond license
<whitequark> can anyone toss me a license or do i have to do the thing again
<whitequark> fucking proprietary tools
<whitequark> i mean i guess thats probably only partially lattice's fault, synopsys and all
<whitequark> but it is no less annoying
<daveshah> To build designs for the SERDES parts you need paid Diamond
<daveshah> But there should be a voucher with your kit
<azonenberg_work> daveshah: oh, that explains why i never used lattice parts
<azonenberg_work> lol
<whitequark> daveshah: yeah but that needs emailing
<whitequark> and its slow
<azonenberg_work> free tools = no serdes
<openfpga-github> libfx2/master 4067898 whitequark: Add a combined DFU+UF2 bootloader as an example....
<openfpga-github> [libfx2] whitequark pushed 1 new commit to master:
<whitequark> its easier to just open binja
<daveshah> azonenberg_work: not as of five hours ago :P
<whitequark> hahaha
<azonenberg_work> daveshah: :p
<azonenberg_work> i meant with the official tools
<azonenberg_work> xilinx webpack works with lots of serdes chips and even some 10G ones
<daveshah> Yeah, idk why lattice even do that
<daveshah> Given they are now giving away these licenses with their $99 dev boards they really don't value them anyway
<azonenberg_work> lol
<whitequark> what the fuck is the diamond rpm
<daveshah> And that is not even part locked
<whitequark> why is everything inside in tar.gzs?!
<azonenberg_work> yeah with xilinx in the past, i've seriously thought about buying a devkit for a high end part just to get the vivado license
<azonenberg_work> then ultrascale came out and i no longer had a reason to want to use a high end 7-series part
<whitequark> daveshah: am i missing something
<azonenberg_work> because the small ultrascales were way bigger and supported by wepback :p
<daveshah> whitequark: the Diamond rpm is definitely strange
<daveshah> I think you just have to extract everything
<whitequark> ...
<daveshah> Are you sure it's not the service pack?
<azonenberg_work> i mean look at the vivado linux installer
<azonenberg_work> it looks like it belongs on windows :p
<whitequark> daveshah: the service pack is in fact extracted
<whitequark> the base rpm is not
<whitequark> i thought alien fucked up, but no, the cpio file in the rpm is exactly ilke that
<daveshah> Yes I think I remember one of the two needing a load of manual extraction
<whitequark> incredible
<whitequark> who makes these things
<daveshah> I guess the post install script is supposed to do it
<whitequark> oh
<whitequark> nope
<whitequark> i think
<azonenberg_work> whitequark, daveshah: reminds me of silego's installer
<whitequark> ah no found the script
<azonenberg_work> at one point, at least, their upgrade tool pull down a couple gigabyte zip file
<azonenberg_work> pulled*
<azonenberg_work> containing a big pile of deb/rpm packages for every supported platform
<daveshah> I suspect whoever did it didn't understand basic information theory
<whitequark> ok, so alien did fuck up
<daveshah> And thought that the more compression the better lol
<azonenberg_work> you had to unzip, install the one you cared about, and delete the rest
<whitequark> why are silicon vendors like that
<whitequark> rhetorical question
<azonenberg_work> whitequark: seriously, i think that people (like most of us in this channel) who are even moderately competent at both HW and SW engineering
<azonenberg_work> are extremely rare
<whitequark> you'd think silicon vendors could hire programmers
<gruetzko-> no
<azonenberg_work> whitequark: more to the point, people who can design hardware and also understand how people will use said hardware
<azonenberg_work> are in extremely short supply
<daveshah> Lattice subcontract most of their software I understand
<daveshah> Radiant was done entirely by subcontractors
<daveshah> This does lead to an even bigger disconnect
<azonenberg_work> daveshah: yeah there's that, there's also super siloed cultures like intel
<azonenberg_work> i like to work on a team where (ideally) everyone does some hw and some sw or, at minimum, the hw and sw teams talk daily
<azonenberg_work> and each understand each others world in detail even if they're not implementing it
<whitequark> daveshah: oh god
<whitequark> that's horrifying
<gruetzko-> hello. at my company i am the hardware team and the software team.
<whitequark> understandable, but also horrifying
<daveshah> They subcontract all their dev boards to Axelsys too
<whitequark> ... it uses flexlm
<whitequark> of COURSE it uses fucking flexlm
<daveshah> Sometimes they don't even follow their own design rules too
<gruetzko-> is flexlm still as lol as it is on irix?
<sorear> question. why *can't* a CDR PLL lock ex nihilo like an ordinary PLL can
<daveshah> whitequark: find one EDA tool that doesn't :P
<daveshah> I was doing an internship at a non-electronic engineering SW company
<daveshah> One of their devs spent the best part of several days on the phone to a uni it guy trying to sort a flexlm server
<daveshah> They could have written a fucking flexlm replacement in that time
<whitequark> amazing
<daveshah> Unfortunately some companies have an idea that everyone runs flexlm so corporate users have a flexlm server set up already so it's all easy
<daveshah> Seems that breaks down due to incompatibilities between flexlm versions anyway
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<sorear> meanwhile somebody apparently got vivado working in docker
<whitequark> ok, at least it's easier to run under gdb than vivado
* whitequark sighs
<whitequark> i hate this.
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<gruetzkopf> i know at least one person to have done that
<gruetzkopf> they docker ALL the things
<whitequark> ...
<whitequark> $ ISP_DBG_LIC=1 ./diamond
<whitequark> For your information: UNIX sk_get_license() Return FALSE, EXIT.
<whitequark> i
<whitequark> incredible
<whitequark> licensing added and removed here.
<gruetzkopf> .
<whitequark> thanks diamond.
<whitequark> yeah that environment variable literally traces every flexlxm call to stdout
<azonenberg_work> loooool
<azonenberg_work> //drm added and removed here
<azonenberg_work> sounds about right
<daveshah> Of course Lattice don't really care about their licensing
<daveshah> If it keeps Synopsys happy it's good enough
<whitequark> i mean, it's one thing to not care, and the other thing to have ISP_DBG_LIC lol
<daveshah> Wouldn't surprise be if ISP_DISABLE_LIC was also an option lol
<gruetzkopf> thats "[✓] Licensing" IDGAF level
<whitequark> doesn't seem to have ISP_DISABLE_LIC