<kbeckmann>
nextpnr-ecp5 question: Is there a convenient way to get around this error? Running into it when writing a FSM that starts getting a bit complex. ERROR: cell type '$_DLATCH_P_' is unsupported (instantiated as '$auto$simplemap.cc:517:simplemap_dlatch$581')
<kbeckmann>
(I'm also a noob so I might be doing something very illegal and triggering this because I don't know what I'm doing)
<kbeckmann>
Happy to post my code but wanted to ask first in case it's a know thing.
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<q3k>
hm
<q3k>
is this for ice40?
<q3k>
looks like you're inferring a dlatch somewhere
<q3k>
which is generally Bad Mojo (tm)
<q3k>
however, this should be handled much nicer by the tooling
<q3k>
ah, ecp5, sorry, just notice
<q3k>
daveshah: ^ sounds like an issue on the yosys side of the ecp5 flow? maybe? i'm not sure what it should do.
<kbeckmann>
Alright. I'm most likely doing something stupid but still interested to know if it's possible to work around somehow :)
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* ZipCPU
discovers whitequarks comment
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<kbeckmann>
Solved my dlatch stuff by not doing stupid stuff so that's cool. However I have some trouble with BIDIR IOs on ECP5. I'm using the following construct.. Is anything missing or looking strange? TRELLIS_IO #(.DIR("BIDIR")) TRELLIS_IO (.I(pin_i),.T(pin_oe),.O(pin_o));
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<kbeckmann>
daveshah: could you explain shortly how BIDIR IOs are supposed to be used? Didn't find any usages in the wild to copy from :)... There are also the ports B, IOLDO and IOLTO. What do they control?
<kbeckmann>
Oh now I see it - B is the actual pin, now I feel a bit stupid for not seeing that before. Getting an assert now, creating an issue for it. I'm however still curious about what IOLDO and IOLTO do.
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<_whitenotifier-6>
[Boneless-CPU] cr1901 opened pull request #1: Merge boneless_sim with Boneless-CPU - https://git.io/fhUyg
<whitequark>
21:56 < TD-Linux> whitequark, did you consider just a shift-by-1 instruction and requiring a software loop?
<whitequark>
yes, but this is fairly bad for code density *and* programmability in assembly
<TD-Linux>
macro assembler? but yea
<whitequark>
remember it runs from one BRAM
<whitequark>
which can be as small as 256 deep
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<_whitenotifier-6>
[Boneless-CPU] whitequark commented on pull request #1: Merge boneless_sim with Boneless-CPU - https://git.io/fhUy6
<_whitenotifier-6>
[Boneless-CPU] whitequark commented on pull request #1: Merge boneless_sim with Boneless-CPU - https://git.io/fhUyP
<marcan>
whitequark: can you implement the shifting using some kind of fetch hack?
<marcan>
like on shift insns, do not increment the program counter until shift_count == whatever the instruction encodes
<marcan>
</random idea>
<marcan>
(not sure what your pipeline looks like, that might be stupid)
<daveshah>
kbeckmann: ad the DLATCH issue, what Yosys version are you on? There was supposed to be support for them (using logic loops so they'll break timing analysis) a while ago
<tnt>
SolraBizna: are you sure ? I just did this quick test case : https://pastebin.com/Ee4L3saS and I would have expected o[1:0] to be directly from i[1:0] but that's not the case, yosys put lut4 in there with i[3:2] as inputs.
<tnt>
Essentially for that test case I would have hope to see only 1 LUT4 for o[3], then o[2:0] = i[2:0] pass-thru.
<SolraBizna>
in my test, I had a simple three-input demuxer
<SolraBizna>
after `synth`, it looked like its logic "didn't care" about the possibility of multiple 1 inputs, but on closer inspection this logic does seem more complex than necessary
<tnt>
:/ That's rather disappointing, I would have hoped that simple comb logic minimization would have works oob.
<SolraBizna>
it seems rather important
<tnt>
Damn, that means I'll most likely have to hand-write/optize the decode logic rather than rely on the tool.
<SolraBizna>
I thought this was one of those things I wouldn't have to do now that tools were doing things for me
<SolraBizna>
This isn't the future I was promised!
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<tnt>
SolraBizna: yeah, I feel cheated too.
<whitequark>
i'm pretty sure this can be improved in yosys fairly straightforwardly
<tnt>
heh, I have no clue whatsoever how yosys does what it does.
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<tnt>
Isn't it abc that's used for logic minimization ?
<daveshah>
The solution would probably to optimise the fine grain $_MUX_ cells
<daveshah>
Between mapping to those and ABC
<kbeckmann>
daveshah: Thanks for your answers! The yosys I'm using is just a few days old but can try again with the latest master.
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<tnt>
daveshah: afaict all the 'x' have been replaced after the first 'ice40_opt' call.
<daveshah>
I haven't looked at the ice40 pass, just generic synthesis of that code
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<jcreus>
just curious, is there a whitepaper about nextpnr internals? I saw some slides but they didn't really talk much about algorithmic details
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<daveshah>
Not yet - on the algorithms side there's little more than any generic paper or textbook would cover
<jcreus>
daveshah: gotcha, thanks. Is it still simulated annealing based like arachne?
<daveshah>
Yes, albeit with a timing heuristic too
<daveshah>
nextpnr is more of a framework than just a set of algorithms, I hope someone will do an analytical placer one day
<daveshah>
There's a reason our placer and router are called placer1 and router1 atm