<daveshah>
> Added iCE40 UltraPlus and removed “MX series” to introductory paragraph
<daveshah>
Apparently there was also an MS series too
<daveshah>
tnt: heh, I guess that was at 34c3
<tnt>
yup.
rohitksingh has quit [Ping timeout: 250 seconds]
rohitksingh has joined ##openfpga
rohitksingh has quit [Ping timeout: 246 seconds]
<azonenberg>
daveshah, tnt: related, i know xilinx killed off the xc7a350t (i guess it was too close to being a kintex?)
<azonenberg>
and the xc2c1024 (probably too massive of a CPLD to be practical)
<azonenberg>
before production, unsure if either taped out as prototypes or not
<daveshah>
Interesting, I've never heard of dead FPGAs outside of Lattice
<daveshah>
Lattice have killed off a lot
<daveshah>
I think there was also going to be a MachXO3H with DSPs and a 3Gbps SERDES
<azonenberg>
From hints i see in the ISE 14.7 install
<azonenberg>
there was going to be a 64-function block xc2c1024
<azonenberg>
with a 144-bit wide zia if i'm reading it right
<azonenberg>
1408 total zia inputs so i guess 1024 dffs and 384 gpios
<azonenberg>
looks like it was going to be a 484-ball device
<azonenberg>
Then the xc7a350t, according to an old copy of DS180 i see floating around, was to have had 348480 logic cells, 54450 slices, 4.7 Mbit lutram, 1040 DSP48, 1030 18kb BRAM, 12 CMTs, one PCIe block, 16 GTPs, and 12 banks totaling 600 GPIO
<azonenberg>
incidentally, there are now two 50-pin banks in the artix-7 ffg1156 that no device bonds out
<azonenberg>
they were going to be used by the 350t but when they killed it, it was too late to move the 200t's largest package to 900 balls or something a little smaller
<GuzTech>
Hmm it says logic utilization N/A in the summary.
<whitequark>
hm.
<GuzTech>
Oh, but in the resource summary it says 345 LEs.
<GuzTech>
The fuck is wrong with the summary reporting in Quartus?
<GuzTech>
So the newest nmigen code might also be good, let me double check.
<GuzTech>
Nope, still zero.
<GuzTech>
It's compiled using Verilog 2001 by default btw.
<GuzTech>
In case it matters.
<GuzTech>
The only warnings are default case missing (which is not a problem since assign a default value already), and overlapping cases in the case statement.
<GuzTech>
The overlapping stuff is just 5'bzzz1z type of stuff, which seems correct to me.
<GuzTech>
It should turn it into a priority encoder.
<whitequark>
yep.
Flea86 has quit [Quit: Goodbye and thanks for all the dirty sand ;-)]
<GuzTech>
Also, \r_o$next gets assigned two default values. I assume that the last value gets assigned to it (because then none of the case statements would work).
<GuzTech>
Maybe Quartus gets confused by that.
<whitequark>
blocking assignments
<daveshah>
Even for non blocking assignments, last assignment wins
<GuzTech>
AFAIK blocking assignments influence the signals that depend on the "blocking" signals, but if you assign two values to the same signal then the last wins, even if it is blocking.
<daveshah>
Yes
<GuzTech>
whitequark: You also have rdport_mem_r_data being written to but never read. Looks like an important signal to me.
<whitequark>
it works both in sim and on hardware...
<whitequark>
i think it's an artifact of nmigen/migen compat layer
<whitequark>
bbl, sleep
<tnt>
verilog has no way to put a 'don't care' bit in a case statement that _only_ matches for the 'case' and not the input vector right ?
<tnt>
like is I use casez(mysig) then a z in the mysig will also be considered a don't care.
Miyu has joined ##openfpga
pie__ has joined ##openfpga
pie___ has quit [Remote host closed the connection]
rohitksingh has joined ##openfpga
pie___ has joined ##openfpga
pie__ has quit [Remote host closed the connection]
oter has joined ##openfpga
Elive_inst_en_18 has joined ##openfpga
Elive_inst_en_18 is now known as edmund
catplant has joined ##openfpga
edmund is now known as edmund20
oter has quit [Quit: My iMac has gone to sleep. ZZZzzz…]