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<mithro> "Removed PLL_DS, SB_MIPI, SB_TMDS, SB_MAC16 primitive details. "
<mithro> I wonder what device had those?
<azonenberg> mithro: something that did video, clearly
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<sorear> fun, I can pretty easily find 2.6, 2.7, and 2.3, but nothing in between
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<daveshah> mithro: it was the ice40mx16k
<daveshah> This was scrapped when Lattice bought SiliconBlue
<daveshah> Although of course the SB_MAC16 reappeared in the Ultra and UltraPlus
<whitequark> 16k?!
<daveshah> Yes
<daveshah> There was also a scrapped hx16k
<daveshah> FPGA archeology is fun
<whitequark> awww
<daveshah> I think Lattice didn't want too much overlap between iCE and their other parts
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<daveshah> My guess from the amount of routing is that iCE fabric is more expensive to make
<sorear> -mx- also doesn't exist anymore?
<daveshah> No, but you can find mention of it in a few places
<daveshah> I don't know if either device ever existed outside of documentation
<daveshah> Or whether like the ecp4 they did ship out some samples at some point
<Flea86> daveshah: Interesting. Any idea why they dropped the ecp4?
<daveshah> Yield and manufacturing cost issues, combined with a move away from trying to compete with Xiltera
<tnt> same topic (ice40mx) was discussed nearly 1 year ago :) (29 Dec 2017)
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<daveshah> mentions it
<daveshah> > Added iCE40 UltraPlus and removed “MX series” to introductory paragraph
<daveshah> Apparently there was also an MS series too
<daveshah> tnt: heh, I guess that was at 34c3
<tnt> yup.
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<azonenberg> daveshah, tnt: related, i know xilinx killed off the xc7a350t (i guess it was too close to being a kintex?)
<azonenberg> and the xc2c1024 (probably too massive of a CPLD to be practical)
<azonenberg> before production, unsure if either taped out as prototypes or not
<daveshah> Interesting, I've never heard of dead FPGAs outside of Lattice
<daveshah> Lattice have killed off a lot
<daveshah> I think there was also going to be a MachXO3H with DSPs and a 3Gbps SERDES
<azonenberg> From hints i see in the ISE 14.7 install
<azonenberg> there was going to be a 64-function block xc2c1024
<azonenberg> with a 144-bit wide zia if i'm reading it right
<azonenberg> 1408 total zia inputs so i guess 1024 dffs and 384 gpios
<azonenberg> looks like it was going to be a 484-ball device
<azonenberg> Then the xc7a350t, according to an old copy of DS180 i see floating around, was to have had 348480 logic cells, 54450 slices, 4.7 Mbit lutram, 1040 DSP48, 1030 18kb BRAM, 12 CMTs, one PCIe block, 16 GTPs, and 12 banks totaling 600 GPIO
<azonenberg> incidentally, there are now two 50-pin banks in the artix-7 ffg1156 that no device bonds out
<azonenberg> they were going to be used by the 350t but when they killed it, it was too late to move the 200t's largest package to 900 balls or something a little smaller
<daveshah> Send an RFQ?
<daveshah> 26 week and 2 day lead time isn't bad for an FPGA that doesn't exist
<whitequark> lol
<tnt> :)
<whitequark> maybe they tape it out real quick
<tnt> It's the 2 days that make all the difference.
<whitequark> 26 weeks sounds about right
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<GuzTech> whitequark: Hey, I'm around if you need to have something synthesized by Quartus again.
<GuzTech> Found any more leads as to why Quartus optimizes away the entire design?
<whitequark> GuzTech: nope, but let me try a known good design, that i just verified in hardware
<GuzTech> I saw that the nmigen output had a few case statements without default values. AFAIK, you always want to avoid that.
<GuzTech> But I don't know if Quartus would optimize that away, or just create latches.
<whitequark> there are never any latches in migen output
<whitequark> on each run of always @*, there is always at least some value assigned to the reg
<whitequark> see the very beginning of every always block
<whitequark> so, it is not necessary to have default values
<GuzTech> Ah yes, you're right. Don't mind me.
<whitequark> try this
<whitequark> iverilog accepts it, yosys ysnthesizes it and it works on hw
<whitequark> you can sim it with quartus too
<whitequark> feed it a few hundred clocks and see that pins will change
<GuzTech> Still optimizes everything away.
<GuzTech> Unfortunately I can't run Modelsim in Quartus because I'm running Arch.
<whitequark> hm, weird.
<whitequark> let me try old migen
<whitequark> what abotu this?
<GuzTech> Hmm, this one actually has registers and BRAM, but still no logic cells: https://paste.gnome.org/pg8taw131/uejzdj
<whitequark> wtf quartus?
<whitequark> wait: Implemented 412 logic cells
<whitequark> that seems about right?
<GuzTech> Hmm it says logic utilization N/A in the summary.
<whitequark> hm.
<GuzTech> Oh, but in the resource summary it says 345 LEs.
<GuzTech> The fuck is wrong with the summary reporting in Quartus?
<GuzTech> So the newest nmigen code might also be good, let me double check.
<GuzTech> Nope, still zero.
<GuzTech> It's compiled using Verilog 2001 by default btw.
<GuzTech> In case it matters.
<GuzTech> The only warnings are default case missing (which is not a problem since assign a default value already), and overlapping cases in the case statement.
<GuzTech> The overlapping stuff is just 5'bzzz1z type of stuff, which seems correct to me.
<GuzTech> It should turn it into a priority encoder.
<whitequark> yep.
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<GuzTech> https://paste.gnome.org/pkcnytdow#line-1189 Which one should be assigned to the next state by default? 4'h1 or state?
<GuzTech> Also, \r_o$next gets assigned two default values. I assume that the last value gets assigned to it (because then none of the case statements would work).
<GuzTech> Maybe Quartus gets confused by that.
<whitequark> blocking assignments
<daveshah> Even for non blocking assignments, last assignment wins
<whitequark> ah huh
<daveshah> This is one way to write resets
<daveshah> As an if block at the end of an always
<daveshah> Instead of an else if
<GuzTech> AFAIK blocking assignments influence the signals that depend on the "blocking" signals, but if you assign two values to the same signal then the last wins, even if it is blocking.
<daveshah> Yes
<GuzTech> whitequark: You also have rdport_mem_r_data being written to but never read. Looks like an important signal to me.
<whitequark> it works both in sim and on hardware...
<whitequark> i think it's an artifact of nmigen/migen compat layer
<whitequark> bbl, sleep
<tnt> verilog has no way to put a 'don't care' bit in a case statement that _only_ matches for the 'case' and not the input vector right ?
<tnt> like is I use casez(mysig) then a z in the mysig will also be considered a don't care.
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<cr1901_modern> https://makingartstudios.itch.io/dls If only this wasn't a game, but generated HDL for FPGAs... the UI is beautiful!
<qu1j0t3> cr1901_modern: haha, yeah :|
<pie___> "YOU THINK THIS IS A GAME!?"
<qu1j0t3> :)
<GuzTech> You think I'm playin?
<qu1j0t3> This could be us, but you plain'
<qu1j0t3> playin*
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<pie___> anyone have an ice40stick for sale at ccc or should I want something else? :p
<daveshah> There will be icebreakers on sale at ccc for 50 euro
<daveshah> Come to openfpga
<cr1901_modern> what's that in usd, like $150 nowadays?
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<daveshah> $56.9 according to Google
<tnt> that's cheaper than the crowdsupply campain.
<daveshah> And it includes EU VAT
<tnt> and shipping
<tnt> (could probably send them through the pneumatic message system :p)
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<daveshah> I don't know how long the 100 will last
<daveshah> I guess we will keep 20 or so so we can keep running the course
<tnt> I didn't see the workshop in the self organized session list.
<daveshah> It's just part of the openfpga assembly
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<cr1901_modern> daveshah: Apropos of my euro comments https://twitter.com/cr1901/status/1076922384840605696
<pie___> daveshah, hmm...on one hand woohooo~ \o/ , on the other hand, usb stick thing :V
* pie___ tapes a icebreaker to his laptop
<daveshah> I guess Fomu wins the USB stick market though
<tnt> pie___: you want an usb stick thing ? I found them inconvenient to have something that large sticking out of my usb port.
<pie___> tnt, makes sense
<pie___> also will definitely visit openfpga place anyway <3
<daveshah> See you there :)
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<noopwafel> yay openfpga assembly \o/ very excited to see that's going to happen
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<pie___> noopwafel, \o/ pretty sure that happened last time too? or was it something else that was kind of also an openfpga assembly
<pie___> cant remember
<tnt> yeah there was an openfpga assembly last year.
<cpresser> assembly-leaks: openfpga has been placed :)
<tnt> and routed ?
* tnt will show himself out
<zkms> :3
<cpresser> the placer will need a few optimization runs
<cpresser> lots of constraints
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<GuzTech> Man, I wanted to go to 35C3 but the tickets sales started so late that the hotel prices jumped up significantly :'(
<GuzTech> So I thought I'd bring up VGA using Clash HDL, and wasted two hours because I didn't properly hook up the 3.3V pin *DOH*
<noopwafel> daveshah: do you have times for the workshop or is it just ad-hoc?
<daveshah> I'm not sure - just come along and either it will be ad hoc or we'll work out times
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<jn__> pie___: i have a icoboard (iCE40 RPi shield) that i'm not using
<pie___> jn__, hm. I mean I probably wont have time any time soon to play with it, so I'm looking for something I can keep
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