##openfpga on 2019-01-01 — irc logs at freenode.irclog.whitequark.org

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00:03 <_whitenotifier-6> [whitequark/Boneless-CPU] whitequark pushed 1 commit to master [+2/-0/±0] https://git.io/fhtE9

00:03 <_whitenotifier-6> [whitequark/Boneless-CPU] whitequark fc5ebcb - Add optimal ALSRU implementation for 4-LUTFF architectures.

00:08 <_whitenotifier-6> [whitequark/Boneless-CPU] whitequark pushed 1 commit to master [+2/-0/±0] https://git.io/fhtE5

00:08 <_whitenotifier-6> [whitequark/Boneless-CPU] whitequark 32debb8 - Add optimal ALSRU implementation for 4-LUTFF architectures.

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00:11 * swetland makes a note to revisit alu design once the guts of his little stack machine prove or disprove usefulness

00:12 <swetland> it's not really a stack machine, I guess, more like register windows + acc + tmp + callstack -- we shall see if it is anything other than a mess

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00:35 <whitequark> swetland: do you think you can beat mine?

00:36 <_whitenotifier-6> [whitequark/Boneless-CPU] whitequark pushed 1 commit to master [+0/-0/±2] https://git.io/fhtuC

00:36 <_whitenotifier-6> [whitequark/Boneless-CPU] whitequark ee0a108 - Update design with LUTFF estimates for new ALSRU design.

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01:32 <swetland> whitequark: ALU? not likely. I was thinking of adopting yours

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01:33 <swetland> will be interesting to do some experiments to look at the delta between the naive big-case-statement and variants and your tuned approach

01:34 <swetland> one thing I like about yosys is being able to pretty trivially synthesize an arbitrary module standalone to get resource counts

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01:44 <whitequark> oh, yeah

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01:57 <swetland> I'm interested in poking at floorplanning / modular design / etc tooling at some point -- especially for larger and more performant parts, the idea of being able to tune and lock down optimized designs for mid-sized blocks and then (probably more rapidly) snap them together seems appealing

01:59 <swetland> and also just some QoL stuff for paths like "synthesize to fpga basic entities, generate verilog, co-simulate and verify equivalent behavior, etc"

02:01 <swetland> like ideally one shouldn't have to know where to find the simulation libraries -- yosys should provide options similar to gcc's -print-libc-file-name -print-sysroot-headers-suffix etc

02:01 <swetland> s/libc/libgcc/

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02:10 <whitequark> hmm, true

02:11 <whitequark> "generate verilog, co-simulate" this is already provided by my equiv_opt pass to some extent

02:13 <swetland> yeah, I'm just thinking of some tooling QoL stuff so things built on top of yosys, etc, don't need to bake in hardcoded paths or copies of libraries or whatnot. Should be pretty straightforward to do. I should poke at it and send some PRs

02:14 <whitequark> I agree

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03:31 <tpw_rules> does hx8k have the large single port ram like up5k?

03:33 <catplant> o

03:33 <catplant> no

03:34 <tpw_rules> i see.

03:35 <tpw_rules> hx8k doesn't have DSPs either?

03:38 <zkms> alas

03:38 <tpw_rules> i've been idly scheming a method by which to implement rANS or tANS on an ice40 but they require quite a large amount of RAM, a multiplier, and divider. up5k isn't fast enough for my input either

03:39 <whitequark> rANS?

03:40 <tpw_rules> an arithmetic-inspired compression scheme

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03:40 <tpw_rules> you said yesterday that up5k can't do a 75MHz clock rate right?

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03:41 <whitequark> it definitely cannot

03:41 <whitequark> not even on a trivial design

03:41 <whitequark> much less a compresison scheme

03:42 <tpw_rules> well i just need a few registers at 75MHz to do some deserializing

03:42 <tpw_rules> the rest only needs to be about 20

03:43 <tpw_rules> or 10

03:44 <tpw_rules> i guess the data sheet is wishful thinking? it says things like 100mhz. i just need a shift register

03:44 <tpw_rules> idk the idea of compression is almost certainly wishful thinking too

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04:30 <xobs> tpw_rules: the usb shift register mithro just rewrote places at around 90 MHz.

04:31 <whitequark> hmmm

04:31 <xobs> it only /needs/ 48 MHz, but nextpnr claims it meets timing all the way up to around 96

04:31 <whitequark> interesting

04:31 <whitequark> worth a try i guess

04:32 <whitequark> maybe nextpnr improved since i tried placing such designs?

04:33 <xobs> well, the shift register is not large, and most of the usb stuff is done in the 12 MHz domain. nextpnr supports multiple clock domains now, which helps quite a bit.

04:33 <whitequark> oh, right

04:33 <whitequark> that was probably why

04:33 <whitequark> tpw_rules: disregard what i said and try it

04:33 <xobs> Info: Max frequency for clock 'clk48': 93.55 MHz (PASS at 48.00 MHz)

04:33 <xobs> Info: Max frequency for clock 'por_clk': 20.12 MHz (PASS at 12.00 MHz)

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15:37 <tpw_rules> ah that's exactly my use case

15:38 <xobs> My goal is to get a Fomu USB bootloader working by LCA, in a few weeks, so I'll be working really hard on it.

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23:21 <azonenberg> mithro, sorear, whitequark: xilinx has an appnote doing CDR on SGMII at 1.25 Gbps in fabric

23:21 <azonenberg> using the iserdes to oversample

23:21 <azonenberg> i personally have done soft cdr on 100base-TX at 125 Mbps but that was on an analog signal

23:21 <azonenberg> sampled at 500 Msps with a 1.5 bit flash ADC :D

23:32 <daveshah> I wonder if the 800MHz max rate of the ECP5 serdes is enough to oversample 480Mbit USB

23:35 <daveshah> Interestingly, the ECP4 was going to have dedicated CDR cores for this purpose

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23:43 <gruetzkopf> ECP4 looks very interesting :|

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