<wizzy>
I need a what I gather is "3D" addressing - I need to access a block as both a horizontal and vertical bitslice.
<ZirconiumX>
wizzy: That's not really how the hardware works, so it's going to be quite expensive
<wizzy>
I implemented it three ways - a for loop in between posedges to calculate the place store [xaddr][y] <= xdata[y]; and ydata [x] <= store[x][yaddr]; to read it out
<wizzy>
it is a messy problem, best done in the grind of latches and gates
<ZirconiumX>
Except without latches because FPGAs hate those
<wizzy>
a 64-way took up 10% of the 7a35
<wizzy>
I thought I knew better - write it as a shift register. There is latency, but none of the read data is valid until all the write data is in
<zyp>
you mean transposing a bit matrix?
<wizzy>
yes. I want to read out all the LSBs of 64 connected integers
<wizzy>
last I looked for some shift register primitives to see there might be some magic
<mwk>
... is xilinx the only vendor that actually does latches
<zyp>
wizzy, why do you need to do that?
<wizzy>
I mean't Dtypes - of course it should be synchronous
<wizzy>
Which was the most efficient of the approaches above ?
<wizzy>
(Hint: I know the answer)
<wizzy>
Is there some butterfly network that could munch a 64-way patch as a series of 16-way patches ? I think you might have to store the whole patch at each step, which would kill it
<froztbyte>
wondering if I want to start counting days this weekend or middle next week ;D
<wizzy>
what to do about booze
<froztbyte>
pretty much gotten to the point of scrounging together whatever I can from the "essentials" list to brew some beer, and I'm strongly leaning to calling it pandemic broth
<froztbyte>
it'll only be done by end of lockdown but hey it'll be a thing to do
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<froztbyte>
(for the viewers at home who may wonder wtf, movement and sale of liquor is entirely banned in ZA during its lockdown)
<wizzy>
ditto cigarettes
<wizzy>
way to get the people on your side
<qu1j0t3>
"your side"?
<qu1j0t3>
there are sides in this lol
<wizzy>
they need people to stay at home. Telling they can't smoke makes them wonder if the same funny reasoning is keeping them home
<wizzy>
back to my slice access above, the block RAM has byte writes, so I could write an imperfect line so long as some bytes were done
<wizzy>
is there a sweet spot on Xilinx for MUX size? If I am going to break it up, it might be helpful
<ZirconiumX>
wizzy: MUX2 or MUX4; the hard muxes can do that, as can the LUTs
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<wizzy>
what are the hard MUXes ?
<wizzy>
I don't think the Artix has it?
<ZirconiumX>
wizzy: The Artix has them, because it's a Series 7 chip
<ZirconiumX>
Xilinx CLBs have LUT6s connected by hard multiplexers to create LUT7s/LUT8s
<ZirconiumX>
Depending on the situation, the compiler can infer you want to use these muxes
<ZirconiumX>
Otherwise, you can fit a soft logic MUX4 in a LUT6
<mwk>
every xilinx chip since the original virtex has hard MUXes
<mwk>
the series 7 maxes out at 16-to-1 mux using a single slice
<mwk>
larger that that, and it needs to combine several slices using general routing
<mwk>
ultrascale maxes out at 32-to-1
<wizzy>
thanks. I am just playing with the tools at the moment - I ordered a dev board but it is stuck in Dubai
<wizzy>
I started with icestorm - which was very impressive to me
<wizzy>
but I downloaded Vivado - which is also great. I love it that it uses tcl
<wizzy>
the simulator, and the Schematic tool - incredible
<whitequark>
Vivado is probably the best proprietary toolchain out there, at least from a major vendor (I can't claim to have tried every one that exits)
<ZirconiumX>
It's a low bar to clear
<ZirconiumX>
wizzy: You can use TCL with Yosys
<ZirconiumX>
But generally you don't really need it
<whitequark>
TCL in Yosys is nowhere near as powerful as in Vivado
<whitequark>
you could use Python in Yosys to get a similar amount of access to the design
<wizzy>
I am still pointing and clicking
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<wizzy>
I see Vivado has provision for an HPC backend