<hackerfoo>
Do you have any input other than "do what nextpnr does?"
<hackerfoo>
I think improving the starting placement might help. Maybe it would be worth running a simplified version of something like HeAP first.
<daveshah>
Yes, that would make sense
<daveshah>
HeAP is not too hard to implement
<daveshah>
nextpnr uses mostly HeAP and then SA with a low, almost zero, temperature for refinement
<daveshah>
Similar to the HeAP paper, where the refinement part is effectively SA with zero temperature
<daveshah>
That paper also describes a parellisation strategy for refinement which might be interesting to play with
OmniMancer has joined ##openfpga
<hackerfoo>
I'd like to be able to use ~64 cores effectively.
<hackerfoo>
That's where high-end desktop/workstations are now, so maybe it will be common in 5 years.
<daveshah>
For a large FPGA, I think that is quite doable
<daveshah>
A lot of the refinement is quite localised
<daveshah>
Consider, splitting a million LUT FPGA into 64 chunks gets you 15k LUTs each, bigger than an iCE40
<daveshah>
Yes there is some cross boundary optimisation to consider but I think it is doable
<daveshah>
At least if you can get enough important data into cache
<hackerfoo>
The obvious way to split the problem would be by clock region, because it makes sense to avoid spreading things across these boundaries anyways. The xc7a200t has 20, bigger chips will have more.
<daveshah>
Yup, bigger devices have SLRs which are a much harder boundary
<daveshah>
Given how expensive routing across SLRs is you want to be pretty careful about the split from the start
<hackerfoo>
But I'm wary of doing anything geometrically, because I don't want to depend on knowledge of the geometry.
<daveshah>
I think in some cases manual partitioning is recommended anyway
<hackerfoo>
Yes. There will be work on constraints in VPR. I'm personally interested in partial configuration, because I think this is what sets FPGAs apart from CPUs and GPUs.
<hackerfoo>
Or ASICs in general
OmniMancer has quit [Quit: Leaving.]
OmniMancer has joined ##openfpga
OmniMancer1 has joined ##openfpga
OmniMancer has quit [Ping timeout: 256 seconds]
jfcaron has quit [Ping timeout: 256 seconds]
Asu has quit [Quit: Konversation terminated!]
somlo has quit [Ping timeout: 265 seconds]
somlo has joined ##openfpga
Bob_Dole has quit [Ping timeout: 260 seconds]
edmund_ has quit [Ping timeout: 250 seconds]
m_w_ has joined ##openfpga
m_w has quit [Ping timeout: 272 seconds]
Bob_Dole has joined ##openfpga
Bob_Dole has quit [Read error: Connection reset by peer]