00:01 <kc8apf> Assuming you have enough money for the license, Vivado has provisions for many such things

12:51 <ZirconiumX> How can I diff VCDs?

12:53 <daveshah> ZirconiumX: https://github.com/YosysHQ/yosys/blob/master/tests/tools/vcd2txt.pl ?

12:53 <ZirconiumX> Ah, thank you

12:53 <daveshah> Not tried it myself but I think the Yosys tests use it to diff them

12:53 <daveshah> It's the statutory perl in Yosys, no EDA tool is complete without it :)

15:26 <_whitenotifier-3> [Boneless-CPU] zignig synchronize pull request #10: Assembler Update - https://git.io/Jff5t

16:03 <ZirconiumX> Internal Error: Sub-system: SGN, File: /quartus/synth/sgn/sgn_utility.cpp, Line: 4893 <-- ah yes, my good old friend, the Quartus ICE unique to me

20:37 <florolf> what is up with those u.fl connector drawings? all of them have a "cut-out prohibition area" or something similar between the GND pads (https://www.jst-mfg.com/product/pdf/eng/eAYU1.pdf?5e9b625486318 https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=C-2337019&DocType=Customer+Drawing&DocLang=English https://media.digikey.com/pdf/Data%20Sheets/Samtec/RSP-122811-01_dwg.pdf)

20:38 <florolf> it's so consistent i assume it has to be a translation artifact, but i still don't know what it's supposed to mean. no copper at all? no bare copper? no traces?

22:14 <awygle> no copper

22:15 <awygle> or it'll disturb the impedance matching

22:15 <awygle> florolf: ^

22:21 <florolf> awygle: hmm. but couldn't they theoretically also be constructed to take a ground pour into consideration? i guess that would be harder to control for, though