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<tnt> ZirconiumX: every time I trieds -retime, the results were either worse or the same so ... I kind of gave up on it.
<daveshah> It's implementation is horribly broken tbh
<daveshah> *its
<tnt> but tbh I'm not all that surprised because I tend to manually properly distribute my pipeline stage in my head ...
<daveshah> Yeah
<daveshah> Fine grain retiming in nextpnr might still be able to give a small improvement
<daveshah> but that's a way off on the TODO list
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<tpw_rules> are there any open risc-v cores with the classic risc pipeline and so can mostly do 1 clock per instruction?
<ZirconiumX> Minerva is not strictly "classic RISC pipeline", but almost
<ZirconiumX> (it's 6-stage)
<tpw_rules> see i was looking at it but it says it has caches and it's not clear what the performance implications are
<tnt> Vex in its full config as well I think.
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