07:33 <cyrozap> I discovered something kind of funny this week

07:34 <cyrozap> I stopped work on the PSoC RE a couple years ago for various reasons, one of which was that my Verilog UDB/PLD model wasn't synthesizing to the correct circuit when I wast testing it.

07:35 <cyrozap> Turns out, it was totally correct--I just wrote the test data wrong :P

07:35 <cyrozap> After fixing the data it worked perfectly.

07:41 <cyrozap> Also, I discovered something else: The dump I had made of the design that I synthesized and flashed to a PSoC had its UDBs totally unconfigured, which puzzled me since that's where the PLDs are, and which was why I manually wrote that test data in the first place. So when I looked at it and cross-referenced the bits set in it with the TRM and the patent diagrams, I realized that my simple "A & B = Q"

07:41 <cyrozap> test case was synthesized to work entirely using the interconnect fabric, without any PLDs being involved at all!

07:43 <cyrozap> So, lessons learned:

07:43 <cyrozap> 1. I really need to RE that interconnect fabric and write some models for it.

07:44 <cyrozap> 2. Test cases should not be trivial like this one.

15:28 <pointfree> o/ cyrozap!

15:36 <pointfree> https://mobile.twitter.com/lowfatcomputing/status/1142283358853971969

15:36 <pointfree> http://www.psoctools.org/psoc5lp-example-configs.html