05:29 <azonenberg> daveshah: that was one problem i had with timing constraints in the xilinx toolchains

05:29 <azonenberg> forcing you to have constraints independent of the rtl

05:29 <azonenberg> very often there are things where i specifically *want* a constraint to follow rtl

05:29 <azonenberg> like a synchronizer IP

05:29 <azonenberg> and i want it to apply to every instance of it

05:29 <azonenberg> so a proper means of putting constraints in verilog attributes would be quite nice

05:47 <whitequark> quartus actually does support that

05:48 <whitequark> their synchronizer IP uses it

05:48 <whitequark> i suspect you could actually do something similar using tcl in xilinx

09:16 <daveshah> LiteX does something like this in fact: https://github.com/enjoy-digital/litex/blob/master/litex/build/xilinx/vivado.py#L269-L286

11:26 <tnt> Wow, the ice40 global buffers are nearly 1.2 ns faster to propagate a falling edge than a rising edge :/ Didn't expect that much of a difference.

11:27 <mwk> ... how did you measure that?

11:27 <tnt> That's what icecube says, I didn't actually measure it.

11:27 <mwk> huh

11:28 <tnt> But if they bothered analyzing rising / falling edge clock path differently, I'd guess they actually spec'd it.

15:27 <whitequark> could be from sim?

15:32 <tnt> sure. Looking at the numbers between global clock input and global buffer from a pll, the former shows much more difference between rising/falling so it's probably something in the IO buffer / threshold that's contributing a lot to it.