08:12 <lambda> I have a case of "it works in simulation but not on hardware" - since there are quite a few steps between VHDL and an xc7 bitstream, I'd like to simulate the post-yosys-synthesis verilog before trying anything else. what's the easiest way to do that? verilator looks like a chore just to set up, and I don't know how I'd even get it to simulate all the primitives.

08:21 <tnt> I use iverilog with the Xilinx libs without too much issues.

08:22 <lambda> tnt: thanks, I'll have a look

08:24 <tnt> lambda: what's the design btw ? Does it involve IOs ?

08:26 <lambda> tnt: a SoC, and while my current problem (one of many, really) is that an IO pin doesn't toggle when it should, I'm pretty sure the issue is somewhere deeper in my design.

09:01 <daveshah> Another useful test is to create an EDIF file using synth_xilinx -edif and build that with Vivado

09:01 <daveshah> That way you can separate out place and route issues

09:03 <daveshah> Then if that fails, trying write_verilog after ghdl, hierarchy, prep and either building or simulating that Verilog can separate out synthesis or frontend issues

09:21 <lambda> daveshah: yeah, I might do that too - it's beginning to look like a regression somewhere in the toolchain, I'm pretty sure the commit I'm at worked correctly at some point