00:03
Richard_Simmons has quit [Ping timeout: 256 seconds]
00:08
emeb has quit [Quit: Leaving.]
00:12
<
tpw_rules >
does the icebreaker have any 5v tolerant inputs?
00:20
emeb_mac has joined ##openfpga
00:42
solo1 has quit [Remote host closed the connection]
00:42
solo1 has joined ##openfpga
01:25
OmniMancer1 has joined ##openfpga
01:31
Bob_Dole has joined ##openfpga
01:51
gregdavill has quit [Ping timeout: 256 seconds]
01:51
gregdavill has joined ##openfpga
02:01
Degi has quit [Ping timeout: 250 seconds]
02:03
Degi has joined ##openfpga
02:32
futarisIRCcloud has quit [Quit: Connection closed for inactivity]
04:51
Bike has quit [Quit: Lost terminal]
06:06
genii has quit [Quit: Morning comes early.... GO LEAFS GO!]
06:23
emeb_mac has quit [Quit: Leaving.]
07:31
rohitksingh has quit [Ping timeout: 256 seconds]
07:59
rohitksingh has joined ##openfpga
08:25
rohitksingh has quit [Ping timeout: 240 seconds]
08:35
rohitksingh has joined ##openfpga
08:40
solo1 has quit [Ping timeout: 240 seconds]
08:41
solo1 has joined ##openfpga
08:48
Asu has joined ##openfpga
09:07
rohitksingh has quit [Ping timeout: 256 seconds]
09:25
rohitksingh has joined ##openfpga
09:48
rohitksingh has quit [Ping timeout: 240 seconds]
11:45
____ has joined ##openfpga
11:47
gregdavill has quit [Ping timeout: 256 seconds]
11:52
____ has quit [Read error: Connection reset by peer]
11:55
____ has joined ##openfpga
12:00
OmniMancer has joined ##openfpga
12:01
OmniMancer1 has quit [Ping timeout: 264 seconds]
12:32
Bike has joined ##openfpga
13:35
_franck_ has quit [Ping timeout: 240 seconds]
14:02
renze_ is now known as renze
14:11
emeb has joined ##openfpga
15:25
solo1 has quit [Ping timeout: 258 seconds]
15:44
_franck_ has joined ##openfpga
16:43
OmniMancer has quit [Quit: Leaving.]
17:09
GenTooMan has quit [Read error: Connection reset by peer]
17:10
GenTooMan has joined ##openfpga
18:40
lolsborn has joined ##openfpga
18:40
lolsborn has quit [Client Quit]
19:02
mumptai has joined ##openfpga
20:03
<
qu1j0t3 >
https://twitter.com/angelina/status/1243964859395592194 "FPGAs are traditionally programmed using hardware description languages, such as Verilog and VHDL, which is notoriously difficult, time-consuming, and error-prone. FPGA manufacturers such as Intel (formerly Altera) and Xilinx now support OpenCL as a high-level alternative. "
20:08
solo1 has joined ##openfpga
20:44
rohitksingh has joined ##openfpga
20:45
emeb_mac has joined ##openfpga
21:15
Bob_Dole has quit [Ping timeout: 240 seconds]
22:06
Bob_Dole has joined ##openfpga
22:36
Asuu has joined ##openfpga
22:39
Asu has quit [Ping timeout: 264 seconds]
22:53
gregdavill has joined ##openfpga
22:59
Richard_Simmons has joined ##openfpga
23:02
Bob_Dole has quit [Ping timeout: 240 seconds]
23:13
Asuu has quit [Ping timeout: 240 seconds]