02:00 <zyp> are there any ecp5 boards with usable IO available for purchase anywhere apart from the official boards from lattice?

02:02 <zyp> I know of the chinese led driver boards (and are awaiting a couple in the mail), but I understand they are set up for output only, and the IO voltage on the other side of the level translators is not what I want

02:03 <zyp> and then there's the elgato camlink which doesn't seem to have any IO apart from HDMI

02:03 <zyp> everything else seems to be «coming soon» or «assemble it yourself»

02:27 <awygle> i am only aware of the lattice boards

05:03 <kc8apf> zyp: https://radiona.org/ulx3s/ usually have a few available if you email them

05:10 <emeb_mac> zyp: I just recently saw someone using those Colorlight boards but replacing the 5V drivers with bidir FET switch chips which fortunately had the same pinout.

05:12 <emeb_mac> these parts: https://www.ti.com/lit/ds/symlink/sn74cbt3245a.pdf

05:39 <TD-Linux> whoa

08:00 <peepsalot> is there any overall side-by-side comparison of various open soft cores out there? with info like feature sets, relative resource usage, etc.?

08:23 <tnt> zyp: and the elgato hdmi is not connected to the fpga directly (there is a hdmi receiver cihp) so you can't even use those for anything else than real hdmi.

08:24 <tnt> peepsalot: not that I know of. There is so much variation ... also depending on the target fpga, resource usage can vary greatly.

08:28 <peepsalot> tnt: i'm mostly curious about particularly small implementations. sort of wondering what the smallest feature set needed to run linux for example.

08:29 <peepsalot> i suppose there's probably some disagreements about who holds the "record"

08:30 <tnt> "particularly small" and "run linux" are not quite the same objective :p

08:32 <tnt> I don't know about other architecture but for RISC-V your best bet is probably the VexRiscv implementation, it can be configured to run linux.

08:34 <tnt> What's your target fpga ?

08:34 <peepsalot> cyclonev / de10-nano

08:38 <tnt> And why do you want to run linux in the first place ? Because other than a cool tech demo, it's going to be fairly useless except in very specific cases (like prototyping a HDL design you want to make an ASIC of or stuff like that).

08:40 <peepsalot> idk, not really a requirement, just learning what options are out there, and trying to get an idea of complexity for such a core

08:40 <peepsalot> also, just remembered I saw this project a while back, time to look at it a bit more: https://opencores.org/projects/up_core_list

08:41 <tnt> mmu-less linux might bring it to a more reasonable overhead. I think I saw some riscv support for that yet but I don't know if anyone has run it on a fpga soft core yet.

08:42 <sorear> you still need 8-16 MB of RAM, which is going to be larger than any reasonable MMU

08:50 <tnt> sorear: well you need that in both cases.

08:51 <tnt> An hyperram controller is not that big. ~ 500 LCs on an ice40. (and half of that is implementing high-speed serdes manually, so on a ecp5 that has it built in, probably 300 LUT/FFs)

08:51 <peepsalot> this table is pretty interesting https://opencores.org/websvn/filedetails?repname=up_core_list&path=%2Fup_core_list%2Ftrunk%2FuP_list_KIPS_per_LUT.pdf

11:14 <peepsalot> are there physical devices being produced by anyone that utilize wishbone bus? or is it all in FPGA at this point?

11:19 <sorear> presumably the allwinner/sunxi socs with the openrisc1200 core

14:38 <emily> people run linux on ecp5 didn't they

14:38 <emily> i distinctly recall seeing a demo of an ecp5 risc-v linux building its own gateware with the foss toolchain

14:42 <tnt> emily: yeah sure.

14:42 <tnt> I haven't seen anyone actuall _do_ anything with it other than start a demo shell though.

14:42 <miek> emily: i saw a demo of the ecp5 building ice40 gateware, might've been that? https://twitter.com/fpga_dave/status/1107648430757871618

14:43 <emily> yep I think so

14:45 <tnt> 3 min just for yosys on a blinky. Not sure how long nextpnr run took.

15:22 <pie_[bnc]> is labview good

15:22 <tpw_rules> i don't think it has morals

15:23 <pie_[bnc]> :p

15:27 <qu1j0t3> good answer

20:23 <cr1901_modern> Oh, hi qu1j0t3, long time no see

20:27 <qu1j0t3> cr1901_modern: o/