<emeb>
Anyone know if ECP5U and ECP5UM are same die, just with the serdes disable at mfg test?
<daveshah>
Based on the pinout sheet and the tile structure, yes
<daveshah>
I don't even know if it is disabled, or just out of spec
<emeb>
would be interesting to see if one could enable the serdes on a 5U part.
<mwk>
huh, are the pins actually bonded out?
<mwk>
xilinx does the same thing (same die, disabled transceivers), but they actually make use of the broken transceivers to bond out more GPIOs instead
<mwk>
(or use a different package with fewer pins in the first place, etc)
<gruetzkopf>
even then the loopback path MAY work
<emeb>
yep
<daveshah>
I'm pretty sure they are bonded because in the pinout file they are reserved not nc
<daveshah>
And have a "pad number" (which I'm pretty sure are die pads) associated with them
<mwk>
gruetzkopf: some loopback paths, perhaps
<mwk>
but note that transceivers require dedicated power pins, which are also missing
<emeb>
Not "missing" - diffed the pinouts of the 5U and 5UM - the serdes I/O is shown as "reserved" on the 5U, and all the power pins for the serdes transceivers are shown as GND connections.
<emeb>
so it might be amusing to probe the serdes VDD pins on a 5U to see if they're actually short to GND or just VDDs unpowered.
<gruetzkopf>
does someone have some and can check if they're connected to the ground net?
<tnt>
Mmm, I happen to have an ECP5 without balls (from a rework) ...
<tnt>
Need to find the pinout ...
<awygle>
Are there 25Fs with serdes?
<daveshah>
Yes
<daveshah>
But not 12Fs
<awygle>
Wink wink nudge nudge lol
<awygle>
Oh yeah I gotta test that pr oops
<daveshah>
Yeah
<daveshah>
Oh that would be great, thanks
<awygle>
Thank you for making it
<awygle>
Been busy not grounding thermal pads and misloading crystals lol
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<daveshah>
lol
<tnt>
VCCHTX0_D0CH0 is not connected to GND on a ECP5U-25F-8MG285C
<daveshah>
Hehe
<emeb>
tnt: if you use your DMMs diode test mode you should be able to check for the ESD diodes on the serdes I/O pins too. That would indicate if they're bonded.
<tnt>
yup, there are ESD diodes
<emeb>
w00t!
<gruetzkopf>
hehe
<emeb>
suggests that they package up everything that passes the wafer probe, then sort 5U vs 5UM at package test.
<gruetzkopf>
depending on how good their process is one might get a fair amount of working transceivers on 5U parts
<emeb>
likely
<emeb>
you might find that some serdes are randomly unusable.
<emeb>
but if your board design is flexible you could just use the ones that actually work.
<emeb>
Reminds me of a trick that Xilinx was doing (may still) - you give them an FPGA bitstream and they would sell you parts that had failed test but would work yours it at reduced cost, but would likely fail if the bitstream changed.
<gruetzkopf>
i'd really like twice as many :|
<azonenberg>
kc8apf: i want jtaghal cross platform capable. Send a PR if you're gonna do the work
<azonenberg>
emeb: my understanding is that easypath is a bit different than that
<azonenberg>
it's not FAILED parts
<azonenberg>
it's a less stringent test
<azonenberg>
they design a test to use stuff your bitstream uses, plus maybe some other "spare" cells
<azonenberg>
the remainder simply isn't tested. So the chip might be totally fine, it might have some bad resources
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<azonenberg>
i.e. it's not a washout from the production test, it's never been through that test routine at all
<emeb>
azonenberg: ah ok
<mwk>
huh? why would they not test a device?
<azonenberg>
mwk: to increase yield
<mwk>
I mean, if it's fully working, they'd be better off selling it as a proper FPGA
<azonenberg>
mwk: yes but the sorting costs money too
<azonenberg>
AIUI easypath is basically a dedicated wafer-or-more production run at the foundry
<emeb>
mwk: a large part of cost of a component is the testing.
<emeb>
tester time is $$$ and FPGAs need a *lot* of test.
<azonenberg>
if you don't need to use 25% of the block ram, don't waste time testing it
* emeb
remembers arguing with test engineers about trimming functional tests down.
<azonenberg>
$sidegigclient's chip does some dirty tricks with array-level redundancy... they don't test all that thoroughly at the test site because a few bad sram cells etc can be found and remapped later on
<azonenberg>
even a bad core can be found and bypassed, as long as there's not too many of them to meet spec
<emeb>
cute trick
<awygle>
I have a theory based on the relative availability numbers of the U and UM chips over time that it took lattice a while to dial in the process for the serdes
<azonenberg>
yes, serdes tend to drive yield
<azonenberg>
especially if you have a lot of them compared to die size
<emeb>
wonder what the failure mode is - not running to full speed? skew? ??
<awygle>
And that now they basically all pass test, and they're actually downchecking perfectly good parts to fill the cheaper SKUs
<awygle>
I also think this is true re: UM-5G vs UM
<gruetzkopf>
i wonder how much fun AMD has with their 128*16GT/s dies
<sorear>
onfi vs managed flash is also an instructive example
<sorear>
with managed flash, you only have to test the controller online because the flash array will get tested on first boot and bad blocks remapped
<srk>
o/ is there an ecp5 in mPciE formfactor?
<gruetzkopf>
mine's not done yet - what other IO do you need?
<gruetzkopf>
also mini or half-mini?
<srk>
some high speed connector would be nice, looks like half mini, not sure
<srk>
yeah, half-mini (currently unused wifi in this notebook)
<srk>
there's some space around so it could be made a bit larger (~1cm)
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<vup>
does anybody know wether the ecp5 serdes can be used as regular gpio's aswell?
<daveshah>
They have a low data rate mode but they are still low voltage differential in that mode