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<sensille> how do i convert the .bit file to mcs? (ecp5/trellis)
<sensille> (or just a raw binary file)
<daveshah> Usually you can just use the bit file as is
<sensille> i've written it to flash and it does not work
<sensille> but now you say that i see a bdb3 in there
<sensille> so strip the comment, prepend some fffff and bitflip each byte might work
<daveshah> The comment doesn't need to be stripped, afaik
<daveshah> Not sure about bit flipping, I've never used the SPI flash boot
<sensille> maybe. sysconfig guide recommends 16 ff before the bdb3
<sensille> in mcs, the bytes are flipped
<sensille> ok, that should be easy enough
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<sensille> stupid me. after erasing the flash first results immediately got better :)
<sensille> i'll still strip the comment, according to docs it's an unnecessary risk
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<ktemkin> (as long as the comments themselves don't contain a sync pattern in 'em, you're fine)
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<Degi> Neato, the FIFO's from nmigen seem to be working above 600 MHz on the ecp5
<daveshah> Seems unlikely
<Degi> I mean a 32 bit counter worked till 800, above that the last bits got buggy
<daveshah> Is this a 5G transceiver part?
<Degi> Yes, speed grade 8
<daveshah> Ah that is slightly more plausible as that means overvolted at 1.2V
<Degi> Hm interesting
<Degi> For some reason the pll lock flickers at 600 MHz (which it didn't do before, though maybe the configuration was different
<daveshah> On regular parts BRAM clock to out time is >5ns so you'd be getting 3x the specification
<daveshah> More like 2ns for the 5G parts at 1.2V
<Degi> Hm doesn't the FIFO use TRELLIS_DPR16X4 instead of memories?
<daveshah> Oh, it it's a small one
<Degi> Even if I make a big fifo on the order of 20000x8 it still uses these
<daveshah> Hmm, not sure how the nmigen FIFO works to know if that is expected or not
<Degi> I mean I guess if there's enough of that free and if that's faster than bram... I tried to compile a 1e6x8 but that took too long
<Degi> Now I added a second PLL and the first one locks fine... weird (maybe I should stop running it out of spec)
<Degi> At 720 MHz, the FIFO or checking mechanism has quite a bunch of errors.
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