15:32 <tpw_rules> so does litepcie actually work with the picoEVB or nitefury or aller artix-7? i see commits related to it only a few days ago

19:00 <_florent_> tpw_rules: yes i'm using it on 7-series since 2014, it's just that things are improved/reorganized a bit. The most up to date project i can point to is: https://github.com/enjoy-digital/netv2, feel free to ask on #litex channel if you need help doing the port to your board (the nice things with PCIe is that porting to a new board is very easy since there are less than 10 IOs in total if you are using PCIe X1 :)).

19:57 <tpw_rules> _florent_: alright, thanks for the information. i was hoping to implement hardware-accelerated zstd/ANS compression

22:00 <tnt> Can the ECP5 differential input buffer self-bias ?

22:00 <tnt> I know the serdes clock input can do that (you can have both the internal 100ohm termination + internal biasing).

22:01 <tnt> but I don't know about the generic io (of the left/right banks obviously)

22:01 <daveshah> I don't think there is any documented biasing

22:01 <daveshah> iirc the ULX3S people had some trouble capacitively coupling HDMI without biasing so I'd say probably external biasing is needed

22:02 <tnt> yeah, I helped them make it work, and that's exaclty why I'm looking if there is a more elegant solution :)

22:03 <tnt> But they were also missing the 3v3 LVPECL termination on the HDMI side.

22:03 <tnt> They haven't tested with the hdmi termination and without biasing AFAIK.

22:31 <emily> q3k: likely relevant https://github.com/YosysHQ/nextpnr/pull/392

22:44 <q3k> thanks! i still didn't find a way to fix it in nixpkgs, currently hacking around by doing some ugly patching in libtrellis