<kbeckmann>
rvense: was afk, did you get it to work?
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<sensille>
so to use a generic ft2232h as a programmer for ecp5 i guess i just wire up TCK, TDI, TDO and TMS like the ecp5 eval board does?
<daveshah>
Yeah
<tnt>
reset_n as well maybe to force reset if needed ?
<tnt>
Not sure if the ecp5 jtag is always active
<daveshah>
I'm pretty sure it is
<daveshah>
Unless you disable it in OTP or something
<daveshah>
There is a setting to enable background reconfig but if disabled all it means is connecting via JTAG forces a reset
<ktemkin>
JTAG is always active, yeah; and it can override / stimulate any of the other configuration control signals, so there shouldn't be a need to hook up anything than the four primary JTAG lines
<tnt>
ok. Yeah I haven't dug in the ECP5 config yet, only the cross link and in that one the pins are dual use.
<ktemkin>
off the top of my head, I don't think the SVF trellis generates issues a REFRESH command, though; so that might need to be injected
<daveshah>
Hmm, I haven't ever had to reset a board
<ktemkin>
I don't know how Necessary (TM) it is; but it's recommended by the little diagram in the sysCONFIG guide for SSPI, so I've assuming it's the Right Thing To Do (TM) and doing it
<sensille>
no messing around with the vendor id of the ftdi?
<daveshah>
Nope, openocd should be fine with it as is
<daveshah>
(you just need to make sure whatever config you use matches the chip)
<daveshah>
Lattice use default vendor IDs too and their programmer should work as is too
<sensille>
i was hoping to do the first test with the vendor tool, but if need be i can try immediately with openocd
<sensille>
ah, great
<daveshah>
ime, Diamond programmer is much more fussy about drivers (you need to disable ftdio_sio in udev or manually) and the like than openocd
<daveshah>
Might be different on Windows though
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<rvense>
kbeckmann: yes, i got it to work and wrote a slightly more advanced blinky over lunch... there's one flashing led and it advances when you press the button..
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<kbeckmann>
cool :)
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<sensille>
yay, it talk to me. my first bga
<gruetzkopf>
o/
<gruetzkopf>
congrats
<sensille>
:)
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<tnt>
So, I'm trying to TX some packets (really just test code) through a 1000-base-x sfp. This is the code I'm testing with : https://pastebin.com/tYSv4yL6
<tnt>
If I just TX K28.5 / D16.2 sequence in a loop, the other side does see a link.
<tnt>
But if I try to actually TX packets with the code above, it doesn't see a link _but_ it actually does see like 3/4 packets (and correct ones AFAICT) just as I plug in the fiber
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<tnt>
nm ... look like you need a 'longish' sequence of K28.5 / D16.2 at the beginning, probably because I'm not actually doing proper autonegotiation.
<whitequark>
tnt: I'm not sure, but have you considered the latency of comma alignment?
<whitequark>
the receiver might have to get at least as many K28.5 as its barrel shifter is wide, so, easily 16
<tnt>
whitequark: yeah, I think it just expect a string a the idle sequence of "some length" during the init. In theory I should send LINK_NOT_AVAILABLE then LINK_CONFIGURATION but I just wanted a quick test. At least now it works with just a longer sequence of IDLE at "boot".
<tnt>
What I'm really trying to have working is the RX side using the hardware CDR module of the crosslink-nx but so far the "Loss-Of-Lock" is stuck high :/
<whitequark>
are you using vendor generators or using the primitives directly?
<tnt>
Using primitive directly.
<tnt>
SGMIICDR to be precise.
<whitequark>
on ECP5, Lattice likes to have undocumented parameters that need to be set to undocumented values for anything to work
<tnt>
I'm starting to wonder if I need to do some init through LMMI for it to do anything at all.
<whitequark>
but not sure about crosslink-nx
<whitequark>
have you looked at what the vendor generators do?
<tnt>
Yup, I copied the undocumented parameters from a PCS core generated with radiant.
<daveshah>
fwiw, the way CrossLink NX bitstreams work Verilog parameters are effectively the same as doing init through LMMI (parameters for IP like CDR don't correspond to the usual frames but to special bus write commands)
<whitequark>
what about ECP5? is it similar?
<daveshah>
No, only EBR init uses the bus write command for ECP5 - the DCU parameters are in the same frames as everything else
<tnt>
daveshah: yeah, that's what I understood from looking at prjoxide doc. I'm not sure all lmmi registers are exposed through config params though.
<daveshah>
No, quite possibly not
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<tnt>
"""KEEP TIS RESET SCHEME !!! otherwize the CDR model will not work as expected. Only after three LMMI writes to the 0x3, 4, 6 regs the CDR reset timing will be launched."""