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<tnt> daveshah: Do you document somewhere the LMMI registers of the hard IPs ? While I'm digging into this, I might as well write docs for it in whatever format prjoxide wants ...
<daveshah> No I don't have any format for that yet
<tnt> Ok, I'll just come up with something ad-hoc and convert later on if need be.
<daveshah> It will probably be easier to do the mappings automatically anyway. But text strings on the actual meaning are useful and easy to copy in later.
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<ZirconiumX> https://pastebin.com/d0M6suKQ <-- this synthesises to latches right? (snippet from some code that breaks Quartus)
<tnt> that's a bit without context. Is that in a process ? where are all those signals from ?
<ZirconiumX> ~~I'm trying to find out right now~~
<tnt> In anycase that's a weird way to write this and hoping for a synthesizer to map that to RAM blocks (I'm assuming) when written like this seems like wishful thinking.
<ZirconiumX> Unfortunately I'm missing a huge amount of context here myself :P
<tnt> tbh that looks like typical code written by a software developper trying to describe the behavior he wants rather than the logic to be built.
<ZirconiumX> I'm kinda in that stage, but I think I'm getting better?
<omnitechnomancer> That is probably not innocent-looking Verilog
<omnitechnomancer> If that is supposed to be memory then that should probably be an FSM doing separate reads and writes
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<mwk> "innocent-looking Verilog" <3
<ZirconiumX> Sure enough, it was a memory
<ZirconiumX> And *oh dear lord*
<ZirconiumX> Does my explanation look okay?
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<tnt> I'm not sure if I should feel better or worse knowing that using the Radiant PCS block results also in no lock for the CDR ...
<omnitechnomancer> I am not the most experienced in digital logic stuff but it seems fine to me
<omnitechnomancer> This does indeed seem like the kind of code an emulator developer or other software person might write, since it is how you would do this sort of thing in software
<daveshah> tnt: haven't looked at the PCS yet but there were a few places (mostly IO) where I have a strong feeling there are Radiant bugs affecting the bitstream
<daveshah> It would only affect a few IO pins in the larger package and I suspect they were never tested
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<daveshah> Similar issues may well be affecting any CDR modes they haven't tested for all I know
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<mwk> battle-tested software
<daveshah> I'm pretty sure there was a lot of high level pressure to release it early in 2019
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<tnt> daveshah: interesting ... maybe I should deconstruct the bitstream and see wtf LMMI reg writes are done in the final stream.
<daveshah> The "programming file utility" in Radiant Programmer is quite handy for that
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<omnitechnomancer> daveshah: how have you been finding Rust?
<daveshah> Been enjoying it overall tbh
<daveshah> The move wasn't nearly as painful as expected really
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<omnitechnomancer> That is good :)
<omnitechnomancer> I have been taking a bit of a break from the FPGA hacking over the holiday
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<omnitechnomancer> I think it fits somewhat well the kind of code that was present in libtrellis
<daveshah> Yup
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<omnitechnomancer> I think to make pyo3 properly a dev dependency one of two things should be done, either add a feature that enables the python module code and it doesnt touch pyo3 at all if it isnt enabled, or split the library into one that does basic bitstream and database manip and an entirely separate one for the fuzzing that uses pyo3 and depends on the former one
<daveshah> I plan to do the latter at some point
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<omnitechnomancer> I also wonder if it is worth trying to find a generic subset of functionality that can be factored out to make a useful base library for multiple projects
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<rombik_su> I wonder, does anybody here have a working Nios II IDE on Linux with Quartus 17 (and up)?
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