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<_florent_> tnt: here is the dump of the Gigabit PHYs registers (PHY0 and PHY1) for the Colorlight 5A 75B V7.0: https://gist.github.com/enjoy-digital/c9c9a8af911ce23164e51e6737d54866
<_florent_> tnt: this seems to make sense, but sorry i don't have the subregisters of reg 18h
<_florent_> tnt: i also switched to zero delay for the RGMII, since you're right, the delay is probably added by the PCB or PHY.
<tnt> _florent_: thanks for the dumps ! Did you notice any change when going to 0 tx delay at all ?
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<tnt> _florent_: btw, I just saw your commit, but you also removed the RX delay. That one should be there. The PHY does indeed delay the clock by ~ 1.2ns. But then the FPGA internal routing also takes 2ns more to route the clock from the clock pad to the clock input of the IO flipflop than it takes to route the data pad to the data input of that FF. So that's a bit _too_ much delay on the clock, hence why you still need the 2ns delay on the data lines for RX.
<tnt> I'm actually surprised it worked at all without rx delays. At least for swetland the no-delay on rx didn't produce anything valid on a 5b-75e v6 board.
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<_florent_> tnt: thanks, yes i'll investigate TX/RX more carefully
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<tnt> I wanted to give it a shot here but it fails timing miserably.
<tnt> Warning: Max frequency for clock '$glbnet$main_crg_clkout': 40.25 MHz (FAIL at 125.00 MHz)
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<_florent_> tnt: there are indeed still large timing violations with Etherbone on ECP5 that i need to analyze, i was just expecting to see some corrupted packets when testing but got ping responding...
<_florent_> tnt: i'll add a disclaimer to the target file to make it clear that it's still a PoC
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<whitequark> daveshah: remember the JTAG over NTSC discussion?
<whitequark> someone just suggested JTAG over D-AMPS, and i think that's actually more cursed
<GenTooMan> I'll refrain from silly comments, which is probably best.
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<whitequark> azonenberg: are there issues with analog parts in BGA?
<whitequark> asking because the otherwise very nice lms7002m is using a SIX ROW QFN
<mossmann> Ick. Multi-row QFNs are the worst.
<q3k> >SIX ROW QFN
<q3k> i uh
<q3k> i was going to say something but then I realized that there's nothing I can say
<whitequark> the predecessor to that chip used a dual row qfn with square/rectangular pads
<whitequark> and i guess they decided it was too easy to solder?
<mossmann> Every pad is a special snowflake.
<GenTooMan> it almost seems like an un-balled BGA with variable pad sizes
<whitequark> from the last time i posted a pic of that
<whitequark> "A) This is definitely an LGA, with a rather loose interpretation of the G
<whitequark> B) The pad layout was clearly done by Hieronymus Bosch"
<tnt> whitequark: the adi9361 is a standard bga ... no idea why lime went with this weird pkg.
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<cpresser> if you actually want to use that device, a kicad-footprint can be made with a generator. this one is pretty close (different pad-types, takes pad-coordinates from a spreadsheet). https://git.aubergine.wtf/cpresser/kicad-footprint-generator/src/branch/intel-bga-1356/scripts/Package_Intel/intel-bga.py
<whitequark> oh, no, i just want to know why the hell they did it
<whitequark> or do you mean the microchip one?
<cpresser> no clue at all why they did it. neither for mircochip, nor for the intel part
<whitequark> someone on twitter mentions that BGA substrate is costly
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