<Marex>
ZirconiumX: quartus really makes me wanna hang myself when working with CV
<Marex>
ZirconiumX: it crunches for minutes only to discover a typo in top.v ...
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<tnt>
Does anyone know if clock gating in FPGA has a significant power gain if the actuall FFs that are clocked are not actually toggling ? (i.e. it's a long arithmetic data path but all data inputs are forced to 0 when inactive)
<keesj>
I don't
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<daveshah>
My gut feeling is that clock gating is going to only really save the global clock tree power usage, the majority of power usage would be logic which wouldn't be consuming anything significant if it isn't toggling
<daveshah>
looking at Diamond Power Calculator, at 100MHz and 25% activity factor; 5000 LUTs and 1000 FFs would use 0.03W (which you would already save just by not toggling); whereas the clock network would use 0.008W (which gating would save too)
<tnt>
daveshah: yeah, that's sort of what I was thinking. And the issue is I can't shutdown _all_ the logic, which mean during the active phase, I'd have to use two clock networks (one for the always on clock and one for the gated one) which might just defeat the whole point ...
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<cpresser>
leakage-current and tunnel-current also are quite significant factors to overall current draw of a chip. its not just the logic toggling
<cpresser>
some arm m0+ cores i have been working with have switches for the clock and power
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<cpresser>
but that does not answer the initial question, on how big the impact of just clock-gating is. doh.
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<bluezinc>
azonenberg: The phase offset is only in your head. Sine waves don't have hair.
<tnt>
cpresser: yeah, the device exist, it's deployed, like the only thing I can change is the gateware on it ...
<tnt>
_florent_: I'm trying to understand why RGMII works in your demo, because AFAICT, TX shouldn't :p
<tnt>
From everything I got so far, there shouldn't be any delay in the phy (i.e. clk edge should be aligned with data edges) because the PHY defaults to the RGMII 'delayed' mode where it expects setup time of -0.9 ns and 2.9ns hold times.
<tnt>
Do you change the phy settings via mdio ?
<_florent_>
tnt: it's probably a bit of luck here, i did a very quick test and should indeed adjust the timings. I only got the first PHY working, i should try with 0 delay on the second one
<_florent_>
tnt: i'm using the default settings of the PHY
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<tnt>
And you're resetting the PHY ? (I figured maybe the default bitstream also might change the phy config before you load your own bitstream via jtag).
<tnt>
I only have the B50610 datasheet, not the B50612, but I figured, they're probably the same ...
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<_florent_>
yes i'm resetting the PHY at startup
<tnt>
Also, interesting is that MDIO has a 10k pullup. But MDC doesn't look like it has one.
<tnt>
(at least on my board)
<tnt>
From looking at LiteEthPHYMDIO, that seems expected, nevermind.
<_florent_>
tnt: i can probably easily dump the phy registers over mdio if that can be useful
<tnt>
_florent_: yeah, that would be useful to confirm things at least.
<_florent_>
tnt: ok, i'll try to do it (but tomorrow)
<tnt>
Ok great. I just had a look and the default bitstream does do some writes to the PHYs.
<tnt>
Only writes to "Reserved" registers ...
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