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<pie_[bnc]> whoa whoa whoa "I'm writing a third edition of Security Engineering, and hope to have it finished by Easter 2020 so it can be in bookstores for Academic Year 2020-1. " new edition of security engineering this year
<pie_[bnc]> "With both the first edition in 2001 and the second edition in 2008, I put six chapters online for free at once, then added the others four years after publication. For the third edition, I've negotiated an agreement with the publisher to put the chapters online for review as I write them. So the book will come out by instalments, like Dickens' novels. Once the manuscript's finished and goes to press, all except seven sample chapters
<pie_[bnc]> will disappear for a commercial period of 42 months. I'm afraid the publishers insist on that. But therearefter the whole book will be free online forever. "
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<futarisIRCcloud> pie_[bnc]: At what URL will it be available at?
<pie_[bnc]> oh sorry
<pie_[bnc]> I thought I posted it
<pie_[bnc]> here's the current stuff (the usual place)
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<omnitechnomancer> whitequark: what is the most reasonable way to use a clone of upstream nmigen, just set PYTHONPATH?
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<whitequark> omnitechnomancer: python3 develop --user
<omnitechnomancer> thank
<mithro> rvense: Ewen on #timvideos channel has been looking at some of the ice40 HX8K stuff the last couple of days for the tinyfpga-bx
<omnitechnomancer> whitequark: oh also apparently there is a set_max_delay SDC constraint command
<omnitechnomancer> doubt there is enough introspection to generate the constraints from tcl though, is it possible to iterate over them in nmigen?
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<keesj> why can we place and route fpga code but not normal pcb?
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<ZirconiumX> keesj: FPGAs have fixed routing and fixed cells in a grid. PCBs are significantly more free-form
<ZirconiumX> It's totally possible to do it automatically - see things like TopoR - but it's a harder problem AIUI
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<tnt> Also fpga have tons of crossing wires ... Given 20 copper layer to an autorouter and it will route your boardd no issue :)
<sorear> And yet ASICs are autorouted fine, despite having a fixed number of layers, costly vias, and free positioning
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<keesj> I guess there is also that the structure of the FPGA (all the same type of stuff) allows to place functionality anywhere but still something like axi bus is quite wide
<sorear> ASICs are even more homogeneous!
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<GenTooMan> a route in simple terms is difficult, then add in things such as controlled impedance, controlled network response and it becomes much more difficult. It's been 40+ years to get things as good as they are, I keep that in mind when thinking about the problems.
<mithro> Does anyone know where Dave Shah's giant ECP5 based board is kept?
<mithro> daveshah: ^
<daveshah> Physically?
<mithro> daveshah: No the design
<mithro> Thanks! For some reason I didn't think to just look at your GitHub user
<TD-Linux> that's a lot of voltage rails
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<mithro> duncan47: Take a look at
<mithro> duncan47: You should also chat with azonenberg -- He does a whole bunch of very interesting FPGA boards around a thing called starship raider IIRC
<mithro> azonenberg: You should chat with duncan47 -- He is very interested in complex FPGA boards and doing automatic layout around them
* swetland is finally getting around to poking at ECP5 this week. fun fun fun
<duncan47> azonenberg We've built a tool for automated software-defined PCB design. Looking for some open-source applications using FPGAs. So if you could have a custom FPGA board generated automatically, what would be on it?
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<azonenberg> mithro: well most of the work on starshipraider is actually in the i/o cells etc
<azonenberg> the fpga board is a pretty generic artix7 based design
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<azonenberg> sorear: asic routing also has (for the most part) a huge number of tiny components
<azonenberg> all vias are blind/buried
<azonenberg> you can put wiring and vias on top of components
<pie_[bnc]> aaa he quit i wanted to ask where the paper is :P
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<swetland> ye gods this lattice ecp5 devboard came in a nesting set of 3 boxes, outermost (digikey) at 5" x 14" x 27"
* swetland builds a shiny new nextpnr-ecp5
<ZirconiumX> Meanwhile I'm doing dumb things with Yosys for fun and profit
<pie_[bnc]> for fun and prophet
<GenTooMan> I guess that would be one way to have an idea what happens next?
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<TD-Linux> swetland, did it come just like mine?
<swetland> TD-Linux: yup, pretty much the same
<swetland> also, goddammit, Lattice, you put *one* pmod port on this thing, you didn't place it at the board edge, and you put a voltage selection jumper between it and the board edge just to further spite me
<TD-Linux> swetland, yeah all of lattice's ecp5 devkits suck :(
<swetland> to be fair their ice40 devkits are terrible too
<swetland> so at least they're consistent ^^
<TD-Linux> the icestick is the only passable one, and it only passes because it's cheap
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<somlo> swetland: is it a versa, or the one with an 85k ecp5 chip, or something else?
<swetland> oh well, I can shoot bitstreams down to it and stuff works, so that's nice enough.
<swetland> the 85k ecp5 evn
<TD-Linux> the ecp5 evm doesn't even include a crystal by default. you have to have it plugged into a non-suspended usb port to get a clock source
<TD-Linux> at least there's a pad to fix that
<daveshah> Agreed about lattice devkits - the most annoying thing on the Versa is that it uses fast left/right IO for the LEDs, DIPs and 14seg
<daveshah> and slow top IO for the pin headers
<daveshah> So no 4:1 or 7:1 or differential inputs on any accessible pins
<swetland> and, for some reason I thought this thing had external ram on it, but no it doesn't
<TD-Linux> but 7 segment laser rangefinding!
<TD-Linux> swetland, daveshah made an addon board for that. but yeah you'd think it would
<daveshah> Beware the FTDI 2nd channel on the EVN is fubared
<TD-Linux> I think the ulx3s is the real ecp5 devkit. but you can't buy one, I had to make mine myself
<daveshah> I think the default config is I2C for some godforsaken reason
<TD-Linux> also I need to ask them about their weird license
<daveshah> To get a UART you need to change some 0R resistors and reprogram the EEPROM
<swetland> head. desk.
<daveshah> Seems like it is electrically wired for I2C and configured in the EEPROM as FIFO
<TD-Linux> on the plus side, the fpga is good :)
<daveshah> No idea how they managed that given FIFO mode isn't even a possibility
<swetland> there's a lot of "wtf were they thinking" about this thing, to be sure
<swetland> wonder if I could build a little HDMI connector PCB for the diff pairs header.
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<swetland> the magic of friction
<daveshah> To be fair on Lattice they are learning, the LIFCL EVN has three sensibly positioned PMOD sockets
<daveshah> I'm optimistic they might have even got the spacing correct for dual PMODs
<swetland> ahaha
<daveshah> I think this is my favourite Lattice "dev kit add on" though
<daveshah> Literally an adafruit sd card breakout with a very expensive bodge wire
<daveshah> (for all this Lattice bashing I love them really :3)
<swetland> I like their fpgas! I do think they have some really screwy ideas about devboard design
<swetland> I was amazed to see NX in QFN packaging
<daveshah> Yeah, it's nice to see someone still really care about small FPGAs
<swetland> the LP5K is pretty amazing for $5
<swetland> nobody else seems to be going after low cost / low power / small size with any seriousness
<daveshah> To be fair some of the new Chinese companies are
<swetland> hey, have you given any thought to a standardized constraints format for nextpnr?
<daveshah> Albeit with a significant number of ex Lattice staff
<daveshah> I had thought about using Python for that
<gruetzkopf> still need to slap a transceiver'd ecp5 onto a mpcie card
<swetland> it seems like each frontend (ice40, xray, ecp5) has one that is kinda like the one the mfg uses
<daveshah> But linking Python is a bit of a pain
<daveshah> and some of the static builds exclude
<swetland> oh I was thinking more just a simple domain specific language
<daveshah> Yes, the aim is to support at least a subset of the vendor constraint format for each arch
<daveshah> That would probably make more sense
<swetland> to cover io/clk assignments
<swetland> supporting a subset of the vendor language helps the transition, but longer term it might be nice to have a simple, sane, neutral way to write these
<daveshah> The problem is coming up with a format that everyone is happy with...
* swetland nods. always the challenge
<daveshah> One option is to copy the big vendors and go for something Tclish
<daveshah> (ticklish?)
<daveshah> But I'd be interested to see other proposals
<daveshah> Once the format is done implementation would be a 30 minute job
<swetland> I've never done anything very fancy -- just pin / iostd / netname -- but I assume since they're basically tcl for xilinx, etc, some people have probably got crazy-ass constraints files with who knows what in 'em
<daveshah> I guess the standard format would want something like
<daveshah> pin assignment
<daveshah> IO standard
<daveshah> Standard IO settings like pullup/down and drive strength
<daveshah> Vendor specific IO attributes (more obscure things like SSTL termination)
<daveshah> clock frequency
<daveshah> perhaps device specific global settings too (obscure things like SPI flash boot frequency)
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<swetland> pin B3 io=LVCMOS33 net=uart_tx
<swetland> basically a bucket of namevalue pairs, with a handful of standard ones, and part/specific ones as need be
<daveshah> I would probably key on "net" and I'd call it port which is more accurate imo
<daveshah> But that kind of thing is sensible enough
<daveshah> something that vaguely interests me is two-layer constraints
<swetland> yeah port is more neutral
<daveshah> so you have a board level file that aliases B3 to PMOD0_0
<daveshah> and then do pin PMOD0_0
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<daveshah> although I know things like (n)Migen do this it would be nice to have it in the PnR tool too
<swetland> oh yeah, that actually would be really nice.
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<azonenberg> daveshah: yeah i did some of that in my thesis work
<kc8apf> TD-Linux: I was just talking with a friend last night about when he had 2 DRAM chips delivered by Arrow. They arrived on a pallet on a flatbed trailer with a forklift to unload it.
<TD-Linux> wat
<gruetzkopf> did they mess up package weight 0.2kg vs 0.2t?
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<azonenberg> kc8apf: wow
<azonenberg> that beats the single spartan-6 in a foot-wide bga tray with massive overpack from avnet
<kc8apf> unclear on what happened
<gruetzkopf> is "ecp5 on mPCIe" still interesting to anyone except me or did you all move to m.2?
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<azonenberg> kc8apf: ordering system screwup?
<azonenberg> like the guy who ordered 5 cases of serological pipettes and got 5 pallets instead
<gruetzkopf> ooh i remember those photos
<gruetzkopf> also meh no serdes on the low pincount packages
<hackerfoo> gruetzkopf (IRC):The advantage of mPCIe is that you can embed a JTAG adapter (like PicoEVB, but I don't think M.2 requires the host to support USB), but I think mPCIe only has a single lane, while M.2 can have up to four.
<gruetzkopf> i know, but my laptop does not have m.2 slots ;)
<gruetzkopf> i'm also not a fan of "let's use 6*u.Fl for the transceiver
<azonenberg> eew u.fl
<azonenberg> its fine for a one-off connection you'll never unmate
<azonenberg> but serdes arent that
<azonenberg> (also u.fl cables are not usually length matched)
<azonenberg> the advantage of using sata cables for random diffpairs is that they're twinax and well length matched, but with commodity pricing
<gruetzkopf> still haven't found a source for bulk sata cable
<azonenberg> no, but you can buy them commodity in common lengths
<gruetzkopf> yeah, up to like 2.5m is easily available
<gruetzkopf> i did see single twinaxes like used in making multilane SAS cables relatively cheaply
<azonenberg> i mean imo if you need to move fast data further than a few meters it should be optic
<azonenberg> and you can get LC-LC cables made any length you want
<gruetzkopf> sure, i can just do that myself
<azonenberg> twinax makes sense for short range applications
<gruetzkopf> or ask to do it for me, they ship from germany
<azonenberg> but i'd never imagine using one to run e.g. 1000base-KX long haul
<azonenberg> yeah i use fs for all of my fiber, they have a warehouse near seattle
<gruetzkopf> those 7m 1000baseKX cables scare me
<gruetzkopf> kinda waiting to see which fpga family capable of pcie gen3x4 hits "fully FOSS flow" first for another stupid idea
<azonenberg> oh?
<azonenberg> i feel like artix7 isnt that far out
<gruetzkopf> found out how to split the PEG interface in my laptop
<azonenberg> pcie bodgewires anyone?
<azonenberg> lain ^
<gruetzkopf> been there, done that
<gruetzkopf> also located a spare REFCLK driver and verified it already
<gruetzkopf> even more weirdly, this laptop also has a spare (chipset) pcie lane in the ODD bay
<gruetzkopf> i also never managed to locate a pcie gen3 switch with public datasheets
<azonenberg> Switch fabrics in general seem to be a dark art
<azonenberg> I had to build my own ethernet switch ip in fpga because i couldnt find any suitable asics with public docs
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