<shapr>
what's that new chip lattice released? Has lattice figured out they should be explicitly OSS friendly?
<ZirconiumX>
The new chip is the Crosslink-NX I think it's called
<ZirconiumX>
And no, but dave's been on the case anyway
<GenTooMan>
Mind if I say "COOL!" loudly? never mind already did it :D
<GenTooMan>
I do think to obscure the internal magic they use they may have gone a bit too far. Then again they likely should never have used JTAG they way they did.
<pie_[bnc]>
are people throwing money at dave yet
<shapr>
which dave? shah?
<OK_b00m3r>
no! they're discreetly tucking it into his underwear.
<pie_[bnc]>
i like big dies and i cannot lie
<pie_[bnc]>
OK_b00m3r: i did not mean it that way :P
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<promach3>
the SPI flash on tinyFPGA BX is not QSPI ?
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<zignig>
promach3: you can use it 1x , 2x and 4x , you just to set it up correctly
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<promach3>
zignig what do you exactly mean by 1x , 2x and 4x ?
<promach3>
I mean does the hardware schematics support QSPI ?
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<zignig>
promach3: @river_bitrday_party , tinybx has single, dual and quad spi hooked up , you need to __init__ the pins.
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<tnt>
Oh, I had never noticed the "High Strength SB_IO". Looks like in some ice40 device / packages, they basically bonded several IO sites to the same physical pins and you can tell it to enable the output drivers of several IO sites at once to increase drive strength to 2x or 3x ...
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<ZirconiumX>
So, an FPGA bit-hacking question: what's the cheapest way of determining if there is more than one set bit in a wire?
<ZirconiumX>
The best I have so far is `|(x & (x - 1))` which still requires the subtraction
<tnt>
Which bit width, which fpga ?
<ZirconiumX>
64-bits, Cyclone V.
<tnt>
Arf, no idea what structure the intel fpgas have.
<ZirconiumX>
LUT6
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<tnt>
I'd try with just doing a first pass taking groups of 6 bits and outputing 00 / 01 / 10 depending on (all zero, exactly 1 bit, > 1 bit). That would be 22 LUTs.
<tnt>
Then you need a few more LUTs to merge the results.
<tnt>
5 LUTs actually, so total 27 LUT6s.
<tnt>
(and 3 level deep logic)
<ZirconiumX>
Well, the combinations I've tried are `((x & (x - 1)) - 1) >> 63` (original code), and `|(x & (x - 1))` ("what if we use or-reduction instead?")
<ZirconiumX>
Mostly I'm trying to reduce the (pretty-long) combinational path.
<tnt>
Is that using yosys synthesis ?
<ZirconiumX>
At present, yeah; Quartus doesn't support out-of-context synthesis like this
<ZirconiumX>
tnt: Due to register packing it's more like 26.5. Neat solution, thank you!
<ZirconiumX>
tnt made a very good suggestion to reduce the area and critical path of a section of combinational logic, but the area of the whole shot way up
<ZirconiumX>
Which I can only assume is because ABC was using some terms in that which it now has to recalculate separately.
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<ZirconiumX>
Well, trying to find the critical path with just Yosys is....painful