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<anticw> daveshah: which part# did you order?
<daveshah> The qfn72
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<daveshah> 220-LIFCL-40-8SG72CES-ND
<gregdavill> Do you think they'll have enough engineering samples?
<daveshah> Not sure
<gregdavill> I'll be starting work on some new PCBs this week for the QFN72 and BGA400 parts.
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<daveshah> Cool!
<gregdavill> Might work on a modified icebreaker design for the QFN.
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<daveshah> Looking forward to them. Do you plan to do something with the dphy too?
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<gregdavill> Hardware wise what is the best way to breakout MIPI signals? Putting a dedicated camera/display FFC lock you down to specific cameras/displays
<daveshah> RPi FFC is perhaps a decent place to start
<daveshah> I think the new 22 pin one is 4 lane too
<daveshah> You can always have an adapter board for other devices
<gregdavill> Yeah, okay
<omnitechnomancer> What does dphy stand for?
<gruetzkopf> electrical interface standard from the unfriendly people at MIPI
<gruetzkopf> modern cell phone cameras and displays use it
<anticw> it's become very common
<gruetzkopf> yeah, but spec documents play hard to find
<anticw> i googled earlier today and found them ... saved the pdf's just in case
<gruetzkopf> ah
<anticw> daveshah: that's quite an expensive part and only 1 in stock ... mouser has none
<daveshah> Given they only got the first working tape out back a month or two ago it's not too bad
<daveshah> The UltraPlus rollout was pretty slow and that was only a few extra hacks on top of an existing part
<anticw> i didn't realize that, i thought they were fairly significant revisions
<gregdavill> The '1' in stock might be to limit customers buying too many, given they're sample parts.
<gregdavill> I need some good names for some new PCB designs for these parts. Any suggestions?
<anticw> how about a color and a sea creature?
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<anticw> gregdavill: re: cam link pkg removal, you used hot air to remove the bgas and avoiding bumping the passives?
<gregdavill> anticw: Continue with the OrangeCrab theme?
<gregdavill> Correct, I had a small nozzle on when attempting to remove the DDR3, so that didn't work very well. Without the nozzle I was able to heat the entire ECP5/FX3 and remove these with twezzers.
<gregdavill> Because I'm also interested in their ECP5 DDR3 implementation in general, not just pinouts, I've also measured all the resistors/capacitors when removing them.
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<anticw> gregdavill: as a theme i quite like it, simple nouns though ... amaranth moreton-bay-bug would be a bit much
* genii ponders purple urchins
<eddyb> lol I was googling for SD card pmods and there's a digilent one on a .ro web store
<eddyb> 53 in stock?!
<eddyb> if I can get some cheap accessories without waiting a while for an order to arrive I might go for it lol
<eddyb> they have tinyfpga BX in stock?!
<eddyb> I feel silly for doing anything on the iCEstick, since my main excuse was I would lose interest by the time I could get new stuff shipped
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<omnitechnomancer> Orange crab sounds rusty :P
<azonenberg> o/ gregdavill - nice to see you on irc, how long have you been in the channel?
<gregdavill> azonenberg: A few months now... but I'm not logged in too often, typically just skim through logs during my commute, it's easier to reach me on twitter/email. :)
<azonenberg> ah i see. I was gonna say, i dont recall seeing you here before
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<omnitechnomancer> I am slightly curious what the FPGA board sipeed hinted at is gonna be, though Chinese FPGA vendors tend to make for hard to find documentation
<anticw> eddyb: tinyfpga bx you can also get from mouser and digikey if that helps
<anticw> i added one to an order recent, it wasn't too expensive and showed up the next morning
<anticw> daveshah: which datasheet did you get that alureg from? or did it come from the tooling? i can't find that specific image in any of the pdfs they have listed
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<tnt> Damn, I sure hope that pricing is only for the eng.samples ...
<daveshah> Yeah, I can't believe it's anywhere near the target price
<daveshah> Although it is in line with what Xilinx charge in single quantity anyway
<daveshah> I hope lattice don't go down that route too though
<tnt> Just ordered a qfn72 and 400 part while there are still some available.
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<daveshah> Looks like it also achieves the dubious feat of being the first fpga reconfigurable over I3C
<daveshah> (not a typo)
<gruetzkopf> aah, mipi..
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<ZirconiumX> So, I idly compiled the same basic PicoSoC design for the Cyclone V and the Cyclone 10GX
<ZirconiumX> The 10GX is twice as fast (by Fmax)
<ZirconiumX> The V is 100MHz and the 10GX is 200MHz
<____> What about 10LP ?
<____> Is it any slower than 10GX?
<ZirconiumX> I would imagine so, but I'll go build it to give you a better answer
<ZirconiumX> AIUI the 10LP is LUT4 based compared to the 10GX's LUT6-based ALM
<____> Oh. That can impact performance for a long carry chains. But afaik RV32 is quite pipelined, maybe it won't be much of a difference.
<ZirconiumX> 75MHz
<ZirconiumX> That's...quite the drop
<____> Definitely
<ZirconiumX> (FWIW, Yosys synthesising for Cyclone V with my new Intel flow gets to about 90MHz)
<____> I guess it's not very LUT4-friendly. Thanks for the answer.
<ZirconiumX> I don't think it's that
<ZirconiumX> Remember this is PicoRV32, designed to fit on the LUT4-based iCE40
<daveshah> I don't think picorv32 was designed with iCE40 in mind
<____> True. But it's more about real estate and pinout, not architectural optimization.
<daveshah> I'm pretty sure the original uses were xc7 (LUT6) and ASICs
<mwk> yeah, the benchmarks in picorv32 are all about series 7
<mwk> (and ultrascale, which eh, same thing)
<ZirconiumX> Okay, fair
<ZirconiumX> ...Surprisingly, the IV GX does better than the 10LP. Maybe I picked a chip that was *too* low power
<ZirconiumX> Yeah, a 1.2V Vcore raises Fmax to 87 MHz, ____
<____> Aha, so it's not purely a LUT size issue.
<eddyb> anticw: where do you live to get mouser/digikey orders the next morning?!
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<OmniMancer> daveshah: if using separate bels for LUTs and FFs would you add pips to represent the FF source MUX?
<daveshah> Yes
<daveshah> (other option would be to give the FF bel two inputs and a parameter to select which one, but that's probably not so neat)
<OmniMancer> well ultimately the config output will need to figure out what to set the mux to anyway, so its just as easy to let routing deal with it
<daveshah> indeed
<OmniMancer> hmmm, I am a bit intrigued by the LSLICE diagram in the datasheet showing the MI signal going into the LUT and also the "output combine logic"
<OmniMancer> though those diagrams are a bit abstract and not the most right to begin with, the clock cannot be set to constants the way sr and ce can, but does have an invert
<tnt> This can fit in a single LUT (per bit) in a S6 right ? I'm not crazy.
<mwk> tnt: correct
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<tnt> Now if I could just find a way to express that such that XST agrees :p
<OmniMancer> daveshah: hmmm, I wonder if I should just add a function for adding the whole plb worth of Bels, since they are a bit less uniform than ECP5 slices
<daveshah> Probably makes sense
<OmniMancer> there are two independent carry chains for example
<OmniMancer> does the database in trellis have the carry chains as fixed connections?
<daveshah> Yes, it does
<OmniMancer> between slices
<OmniMancer> That might need a "fuzzer" to just analytically add those for eagle
<daveshah> I had to do similar for ECP5 - I think because of their cross tile nature they weren't picked up in the tcl
<OmniMancer> ah yep, I don't think they show up in a meaningful way in pnl, I think it might make nets for the carries that just don't have any routing
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<OmniMancer> oh your carries go sideways
<daveshah> ECP5 is rotated 90° to most FPGAs
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<OmniMancer> indeed
<OmniMancer> daveshah: I suppose I need an extra level of location to deal with the whole two of everything per slice thing
<daveshah> That's usually what 'z' is used for
<OmniMancer> Well I could make z twice as large
<daveshah> For example you could do z = (index of slice) * 4 + (index in slice) * 2 + (ff or lut ? 1 : 0)
<OmniMancer> do the locations have to be unique?
<daveshah> Yes
<OmniMancer> or can two things have the same location if they do not have the same type?
<daveshah> No, locations need to be unique
<daveshah> see the final "(ff or lut ? 1 : 0)" as an example of how to deal with that
<OmniMancer> yes I see that, okay I will make a helper for working out z
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<OmniMancer> daveshah: should I add CLK, SR, CE inputs for each FF then use validity checks to ensure they actually get set the same within a slice?
<daveshah> Yes, that is what I would do
<OmniMancer> Or I guess I can just add pips that only connect them to the input wires that work
<daveshah> You still need a validity check for the placer
<OmniMancer> ah yes indeed
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<OmniMancer> placer needs to know that it places things in routable way right?
<daveshah> Indeed
<mbock> Hi. I am looking for a prebuilt Windows version of nextpnr as well as a way to build nextpnr for Windows, preferably on a Linux machine.
<whitequark> I think nextpnr should be fairly easy to cross-build but I can try and make it even easier by using some of my old CMake cross-compilation scripts
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<mbock> daveshah: Great! Thank you. I will try those (i.e. the first one since I use iCE40 FPGAs).
<OmniMancer> daveshah: so in the separate Bels for FFs model the MI input would not be a Bel input at all but just another wire that has routing in the tile?
<daveshah> yep
<OmniMancer> cool, does it matter what order wires get added in?
<daveshah> No, it doesn't, afaik
<mbock> whitequark: I would be interested in your cross-compilation scripts. Do you want to send them to me via email?
<whitequark> there's not much to it, mostly these toolchain files:
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<OmniMancer> daveshah: does including the FCI/FCO inside the tile have any particular purpose?
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<daveshah> OmniMancer: it means the router will complain if the carry chain is placed incorrectly
<daveshah> if you just drop the carry wire and net, then nothing checks that the placement is actually correct
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<OmniMancer> can relative constraints and validity checks in placement not account for this?
<daveshah> They should do
<daveshah> But if you got your relative constraints wrong then nothing would tell you
<daveshah> Validity checks could deal with it too though
<OmniMancer> I can add them later I guess
<OmniMancer> I would probably need to add fictional FCO FCI to each LUT and hook them up when adding the slice
<daveshah> Yeah
<OmniMancer> and then the ends just kind of connect to the outside world
<mbock> whitequark: Thanks for the link. I'm not very experienced with cmake, do I simply prepend those options to the CMakeLists.txt ?
<whitequark> no, toolchains are a special case
<whitequark> use `cmake .. -DCMAKE_TOOLCHAIN_FILE=../cmake/Toolchain-mingw32.cmake`
<whitequark> and you have to do this in a fresh build directory
<whitequark> (or if you're doing in-tree builds--not recommended--in a clean tree)
<mbock> whitequark: Alright. I'll try this... Thank you!
<tpw_rules> whitequark: in boneless, is ANDI dest, src, 0xFFFF any faster than AND dest, src, src? it does have to do one less memory access
<tpw_rules> also i tried to update design.ods on my computer but i installed the latest openoffice and it crashes repeatedly
<whitequark> tpw_rules: in the current design they're the same
<whitequark> re openoffice: do you mean libreoffice?
<tpw_rules> no i used openoffice
<whitequark> oh
<whitequark> openoffice is oracle's dead fork
<whitequark> well technically libreoffice is the fork but you get the idea
<tpw_rules> oh ok. that's what i used 6 years ago but i guess times have changed
<tpw_rules> would you recommend one of those ands over the other for register copies?
<whitequark> it... looks like there's no openoffice anymore? oracle dumped their codebase over to apache where it rots now
<whitequark> ands? hm
<whitequark> the problem with all of them is they change flags
<tpw_rules> yes
<whitequark> not sure tbh. for now let's say any suitable instruction works as a mov
<tpw_rules> i mean i just downloaded what claimed to be the latest release as of september 21st. but i'm getting libreoffice now
<tpw_rules> alright, sounds good. i was considering which to enshrine in my register allocator. it's an easy change later though
<whitequark> >Oracle announced in April 2011 that it was ending its development of and would lay off the majority of its paid developers.
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<tpw_rules> but i have to teach it a canonical mov to recognize. i was gonna alias whatever got chosen to a COPY pseudo-insn
<whitequark> hm
<whitequark> lol
<tpw_rules> one of the reasons i chose a new pseudo-insn is that i use e.g. ANDI x, x, x to set the flags based on x, and having that optimized away by the register allocator would be awkward
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<whitequark> yes, a MOV pseudo seems more than fine
<cr1901_modern> openoffice got new updates recently (as in a few months ago), but when I finally needed to upgrade my embarrassingly ancient version a few weeks ago, I swapped to libre
<eddyb> just ordered a microSD pmod and a VGA one
<eddyb> I was going just get the former but then I realized that I can hook up the latter to the iCEstick's single pmod header and just get less colors out of it, so the temptation was really strong :P
<eddyb> maybe I can make a tetris or something
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<OmniMancer> I should make something interesting for the 800x480 lcd panel I have for the Tang Primer, something to test flows on would be good
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<tpw_rules> i am always a huge fan of plasma effects
<tpw_rules> which are easy if you have sufficient BRAM and multipliers :P
<OmniMancer> well I am beginning with LUTs and FFs, but once that is working BRAM should be okay to do and the DSPs exist
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<OmniMancer> this can be a tomorrow problem
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<_whitenotifier-5> [Boneless-CPU] tpwrules synchronize pull request #5: Boneless Manual Improvements -
<tpw_rules> whitequark: ^ it is done and ready to be merged
<tpw_rules> hopefully i was concise enough
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<eddyb> would a boneless book be paperback?
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<pie__> bound in animal skin
<OK_b00m3r> hahahaha
<OK_b00m3r> eddyb: :)
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<OK_b00m3r> eddyb: It still has a spine though
<eddyb> oh right that's what I was trying to remember
<OK_b00m3r> just no hide
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<sorear> counterpoint: spiral-bound and binder books
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<OK_b00m3r> binders have spines
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<anticw> eddyb: i'm in the bay area, digikey isn't always next morning but sometimes is ... they ship from MN i think ... not sure about mouser
<anticw> eddyb: ok, looked... last shipment from mouser came out of TX
<daveshah> My Crosslink NX samples claim to have shipped
<daveshah> still showing as 1 in stock so I guess it is 1 per customer
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<azonenberg> sorear, eddyb: a boneless book doesn't have a comb binding, spiral binding, etc
<azonenberg> just pieces of paper sewn/glued together
<cr1901_modern> >boneless book
<cr1901_modern> You mean spineless?
* cr1901_modern creates a repo called Spineless-CPU
<sorear> we already have one spineless tagless G-machine
<cr1901_modern> >Peyton Jones... gee, wonder where I've heard that name before
<cr1901_modern> Guessing "spineless" in this context doesn't mean cowardly
<emily> cr1901_modern: where have you heard it before?
<emily> (if Haskell, well - the STG machine was designed for Haskell, so :) )
<cr1901_modern> emily: Haskell creator, and all-around Functional Programming enthusiast
<emily> daveshah: no dev boards at this point, I'm assuming? (...this is my first FPGA line launch, so apologies if this question is too obvious ^^; )
<daveshah> emily: they are on mouser, but not in stock
<emily> "Haskell creator" isn't quite true, I'm not sure he was even on the original committee? "lead GHC developer/maintainer" is more accurate
<emily> if you want to ascribe Haskell-the-language to one single person it'd be Lennart Augustsson
<cr1901_modern> emily: Oh, oops :P
<cr1901_modern> emily: I would be interested in a portable Reduceron implementation, but it requires a beefy FPGA
<sorear> is he still around? haven't checked #haskell in a decade
<daveshah> don't know whether they will be in stock tomorrow or in 3 months time, who knows
<emily> but in reality it's a design-by-committee merger of a few previous languages with one initial new feature (typeclasses) that has evolved organically through research from there
<emily> sorear: augustss? he's around in general and writes Haskell for a living, I think
<emily> dunno about IRC
<emily> I believe he's still at Standard Chartered?
<emily> cr1901_modern: I'm interested in purely-functional graph reduction parallel wavefront hardware... so maybe I'll produce something interesting if/when I'm actually any good at EDA
<emily> sorear: never mind, he's at X apparently
<emily> with sigfpe I guess
<emily> I've heard they're working on some secret HDL project
<sorear> when are we going to get Alphabet Wayland
<emily> wouldn't be surprised if it's Haskell-y
<emily> (I'd heard that rumour before but forgot about it until now)
<emily> (re: FP people working on HDL at X)
<emily> also sorry for the very-offtopic... >_>
<cr1901_modern> the hell is Alphabet Wayland?
<genii> I'd surmise Wayland rendering system but for Android/ChromeOS
<sorear> cr1901_modern: a bad joke
<sorear> cr1901_modern: emily is talking about Google (presumably now Alphabet) X, the research organization, but X is being replaced amirite
<emily> yeah it's just called "X" these days
<emily> kind of annoying
<emily> oh, "X Development" apparently
<sorear> (still kinda trippy that Dracut, Weston, and Wayland are actual places)
<rvense> i always loved listening to peyton jones's talks, even if i never do much haskell.
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<OK_b00m3r> sorear: ... isn't that how those projects get their names? See also Intel CPUs and Apple operating systems and...
<cr1901_modern> Yes, I want to take my next vacation at 8088
<OK_b00m3r> cr1901_modern: You know what I mean :-)
<cr1901_modern> Sure, I couldn't resist
<OK_b00m3r> nor could I
<OK_b00m3r> irc stands for Poor Impulse Control
<sorear> not really vacation places
<cr1901_modern> I agree... 8088 is probably the name of an asteroid somewhere
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<gregdavill> davidshah: My DK order for the 72/400 parts has also been marked as shipped. Time for me to speed up on those board designs..
<daveshah> Yeah I gotta right some tooling now
<daveshah> Calling the project oxide is now an excuse to learn rust first though :D
<OK_b00m3r> sorear: they are if you're a skier or a hiker!
<sorear> you can’t really ski in weston ma
<sorear> it’s a random suburb, not a resort town
<gregdavill> For my breakout boards, my current working names are: ArcticKoala (similar to the icebreaker for the QFN72), CrimsonGazelle (Redesign of ButterStick for the 400BGA)
<eddyb> daveshah: I really should just have "rust" set to ping me in channels I don't always read everything, I almost missed that :P
<eddyb> actually I regret saying anything already, this is just going to lead in nerdbaiting, lol
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<futarisIRCcloud> Is Project Oxide working with Oxide Computer ( ) ?
<daveshah> No
<daveshah> It's a reference to the fdsoi technology
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<cr1901_modern> whitequark or tpw_rules: Is boneless' ISA finalized yet?
<TD-Linux> I've been using cortex-m-rtfm recently and it's quite nice. sometime I need to make an interrupt controller for risc-v that's compatible with its model
<anticw> daveshah: digikey ships to you from the US or locally?
<daveshah> anticw: from the US
<daveshah> But usually only a couple of days, it's UPS and DDP so tax paid at time of ordering
<daveshah> No handling fees that way either which is nice
<zignig> cr1901_modern: getting closer, tpw_rules just posted the spread sheet update.
<zignig> daveshah: how different is the Nexus from ecp5 or ice40 ? is it going to be a massive pain to reverse engineer ?
<zignig> or does that remain to be seen.
<daveshah> The bitstream is very similar to ECP5
<daveshah> The fabric has some small changes, similar to the difference between xo2 and ECP5
<daveshah> The main pain is the toolchain is different so all the fuzzers need a total rework
<daveshah> (Radiant now not Diamond)
<daveshah> The iCE40 arch has been thrown away as expected - it was a SiliconBlue thing that Lattice acquired but I don't think ever fully understood
<futarisIRCcloud> TD-Linux cortex-m-rtfm does look good.
<daveshah> I think the only thing from the iCE40 that they've vaguely kept are the I2C core and a 10kHz oscillator
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<TD-Linux> futarisIRCcloud, it's cool in that it's the only sane way I've ever seen to use cortex's 16 levels of interrupt preemption
<TD-Linux> it's hard enough to get interrupt handling or signals correct with 1 level...
<futarisIRCcloud> agreed
<zignig> looks like a nice platform , lots of nice phat multipliers and lots or ram.
<zignig> i'm not sure what a LRAM is , but there is lots of it :)
<daveshah> LRAM -> large ram :)
<daveshah> Successor to the iCE40 SPRAM
<daveshah> Still a single port SRAM array, internally double pumped to simulate two ports (like Xilinx UltraRAM)
<daveshah> So it now has two read write ports but still only one shared clock
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<zignig> so not initializable in the bitstream lin SPRAM ?
<zignig> *like
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<daveshah> I think it is initializable in the bitstream
<zignig> cool.
<daveshah> It looks like there's a new command for initialising LRAM, writing pcie config and various other special things
<daveshah> It's a lot of these little things that are nice improvements over previous Lattice arches
<zignig> I just wish they would just release the bit stream format directly. They so miss the point on opensource.
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<daveshah> Pedantically they do release the bitstream format
<daveshah> in the sysCONFIG user guide
<daveshah> They just don't tell you what the bits mean
<zignig> :) indeed.
<zignig> still a 17k and 39k luts is enough space for _big_stuff_
<daveshah> It's not 39k LUTs
<daveshah> Because of the 1.2x effectiveness factor
<daveshah> It's actually about 32x
<daveshah> I don't know where the effectiveness factor has come from, it's bad enough the LUT6 FPGAs doing it but for LUT4 it has no meaning
<cr1901_modern> they're using kibiLUTs
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<daveshah> lol
<daveshah> I've also never heard of it being called an effectiveness factor before
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<daveshah> But marketing factor probably didn't sound so good
<mwk> > I don't know where the effectiveness factor has come from
<TD-Linux> we should clearly measure in "equivalent GALs" instead
<mwk> it is computed by the ancient method of anal extraction
<daveshah> They've actually removed a mux from the slice compared to ECP5, afaics
<daveshah> I can only presume the factor refers to the hard PCIe and MIPI IP
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