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<omnitechnomancer>
daveshah: why does ecp5 pseudo dual port distributed RAM require 6 slices for 16x4 bits?
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<omnitechnomancer>
Oh that is to have both an RW port and an R port
<omnitechnomancer>
So it just does two RAMs and ties the write ports together
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<daveshah>
Yes, that's right
<daveshah>
It's 3 slices (6 LUTs) not 6 slices
<daveshah>
The top one is indeed used to provide the write port signals
<omnitechnomancer>
daveshah: I mean it says 3 for single port and 6 for pseudo dual port, but reading the datasheet more it counts single port as both a read and a write port
<omnitechnomancer>
so to make a ram with a RW port and a RO port you have to double them up and tie the write ports together
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<omnitechnomancer>
daveshah: I have a suspicion that while the datasheet claims you can combine two lslices into a LUT7 that this is not actually done by the tools in any case and may not actually be working
<daveshah>
Seems quite possible
<daveshah>
Have you tried something like a 16:1 mux as input verilog?
<daveshah>
that is the most obvious candidate to map to such a structure
<omnitechnomancer>
I will try, I have been trying to find an expression that you cant factor into a smaller number of LUT4s
<omnitechnomancer>
is building it out of a tree of mux2s reasonable?
<omnitechnomancer>
It appears to synth my tree of ? :s into 12 luts
<daveshah>
Yeah, sounds like it isn't using the large LUT muxes
<daveshah>
The other option might be to try a simple x[sel] style mux
<omnitechnomancer>
That style also uses 12 luts
<mithro>
mwk: Would you be free at say 6:00pm to chat?
<mwk>
sounds ok
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<mwk>
mithro: so?
<mithro>
I'm stuck at the hardware hacking assembly due to people wanting to pick up Fomu hardware -- would you be able to come to me?
<tnt>
Mmm ... you can't control DIFFRESISTOR per pin on the NX ?!?
<mwk>
mithro: so where exactly are you?
<mithro>
mwk: Hardware Hacking Assembly next to the kit selling tables to the right of the stage (while looking at the stage)
<daveshah>
tnt: what do you mean? I found the bit for it alright
<daveshah>
It is per pair like it was for ECP5
<daveshah>
You sure you aren't confused with TERMINATION (which is for SE stuff like DDR3 data lines)