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<OmniMancer>
daveshah: does libtrellis have any way to delete arcs from a mux?
<daveshah>
OmniMancer: no, looks like it doesn't
<daveshah>
Would be easy to add
<OmniMancer>
I have added one to my libtang version
<OmniMancer>
is it normal for compiling the python bindings for libtrellis to consume 2.5GiB?
<daveshah>
Probably
<OmniMancer>
mildly concerning, I guess this is what happens when one uses template magic for code generation
<OmniMancer>
Do bels have a significant overhead in the generic backend, or is it just the wire names?
<OmniMancer>
I am hesitant to try and add the other half of the slices since it already uses 3GiB to load what is already here
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<OmniMancer>
daveshah: what is the routing graph in libtrellis for?
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<daveshah>
OmniMancer: part of the process for generated deduplicated chip databases
<daveshah>
Bels are insignificant because there are so few of them compared to pips
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<OmniMancer>
currently I have only told it about the MSlices and the attosoc uses half of them, but I think my interconnect fuzzing methodology needs some work since some pips are invalid
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<OmniMancer>
daveshah: what assumptions about flipflops does the generic backend make?
<daveshah>
Assuming you are using the generic packer; it assumes they are simple rising edge clocked DFFs with no set/reset or CEN
<OmniMancer>
and it assumes their starting state is reset?
<daveshah>
The sim model uses that
<daveshah>
But nextpnr doesn't really care about that - the synth script doesn't do anything with init either iirc
<OmniMancer>
just figuring out how to map the GENERIC_SLICE onto an mslice in a pnl file
<OmniMancer>
it would be nice if yosys could be made to produce init's as wide as they are supposed to be
<OmniMancer>
daveshah: why does the generic VCC and generic GND init look like this: x14y68_SLICE1.INIT[15:0] = 16'b00000000000000000000000000000000
<OmniMancer>
and x11y67_SLICE0.INIT[15:0] = 16'b00000000000000000000000000000001
<daveshah>
Oh, it was assuming that LUT inputs are default-zero; that should probably be changed to duplicate instead
<daveshah>
iirc pepijndevos looked at that one too?
<OmniMancer>
also why is it 32 bits wide?
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<daveshah>
Probably because something just uses an int somewhere
<OmniMancer>
in my case for attosoc atleast it appears that the VCC and GND are not used so I have just made my converter throw away these slices
<OmniMancer>
what does verilog do if you supply extra numbers in a literal btw?
<daveshah>
doesn't seem to care...
<OmniMancer>
I am now at the point where I just need to deal with generic IOBs and I can see if it works
<OmniMancer>
hoping that no timing is violated :P
<daveshah>
Cool!
<daveshah>
ime on these simple arches hold time isn't a big issue
<daveshah>
I've had no trouble with attosoc without global clocks on ice40 or ecp5
<OmniMancer>
cool
<OmniMancer>
what does the trellis tinyfpga example expect?
<daveshah>
just a clock and single LED
<OmniMancer>
I mean what clock rate is the clock running at
<daveshah>
48MHz iir
<daveshah>
iirc
<OmniMancer>
ah okay, so there is a bit more division than necessary for my board but it should be okay I hope
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<OmniMancer>
hmmmm, well the LED lights (assuming this is due to the signal having the usual sense but the LED being active low)
<OmniMancer>
so likely still some issues to work out
<OmniMancer>
I will try my simple connect the button to the LED design tomorrow
<OmniMancer>
that should let me know if the routing is generally okay
<OmniMancer>
I will also calculate the correct division for the clock
<OmniMancer>
daveshah: what clock rate is the picorv32 in attosoc aiming to run at?
<daveshah>
Pretty flexible
<daveshah>
16MHz+ for useful blinkenlights
<OmniMancer>
and if you only have 1 LED?
<OmniMancer>
I noticed the tinyfpga has a pre divider
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<OmniMancer>
an 18 bit counter, which seems a bit much
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<OmniMancer>
anyway goodnight
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