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<omnitechnomancer> Anyone want to help with the puzzle of where do all the weird extra tiles live in the bitstream at some point?
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<omnitechnomancer> daveshah: does trellis ever have a situation where a tile contains no config bits but needs fixed connections?
<daveshah> I don't think I've ever seen that but it's entirely possible
<omnitechnomancer> So far as I can tell right now the ADC in the eagle doesn't seem to have any config bits by itself, but I need somewhere to record the mapping between the routing inputs/outputs and it's signals
<daveshah> Yes, probably makes sense in the ADC tile
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<omnitechnomancer> I think the channel enables do something in the IO tiles that correspond to the ADC inputs
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<kc8apf> has anyone poked at MachXO3?
<daveshah> In no great way but I understand just from how it's treated by Diamond that it's very similar to xo2
<omnitechnomancer> they're up to 3 already?
<daveshah> They have been for ages (xo3 is similar age to ecp5 iirc)
<omnitechnomancer> ah
<daveshah> There's a fairly new xo3d that has hardware security stuff
<daveshah> hard AES/hash/ecdsa/whatever block and bitstream authentication (as well as encryption which they've always had)
<kc8apf> hmm, I hadn't seen xo3d
<kc8apf> that's very relevant to a discussion I'm having about a security review
<daveshah> As far as I know all of the new features are also in the CrossLink NX (you can see the hard security block primitive in Radiant), but aren't documented as such for some reason
<kc8apf> aha. MachXO3D is being promoted as a component for NIST 800-193 (Platform Firmware Resiliance) solutions
<kc8apf> it's going to get a _lot_ of scrutiny
<davidc__> Everyone knows that FIPS-140 always results in perfectly secure hardware
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