<davidc__>
tnt: well, not the BSDL alone. Combine it with netlist data to produce a list of intended connections, then generate test vectors from that
<davidc__>
tnt: dunno exactly which closed/open source software does it; but I do know it is done
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<whitequark>
daveshah: does nextpnr-ecp5 support routing LDR signals to/from SERDES pins?
<whitequark>
and if yes how?
<daveshah>
You mean the low speed signals?
<daveshah>
For those you need to instantiate a serdes primitive and use the LDR related pins
<daveshah>
(I think assert eg CH0_FFC_LDR_CORE2TX_EN and then drive CH0_LDR_CORE2TX)
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<tnt>
davidc__: yeah I was wondering if there was an existing software that would just try to toggle every pin and tell me if (1) it's stuck high / low and (2) if that made another pin toggle or not or something simple like that.
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<whitequark>
daveshah: yeah. asking because there are no hits for "LDR" in prjtrellis except for DCU.CHx_LDR_CORE2TX_SEL and DCU.CHx_LDR_RX2CORE_SEL
<whitequark>
i'm poking the SERDES with a fast sampling scope and locking the scope to the clock proves a bit difficult
<whitequark>
lattice devboards aren't helping
<whitequark>
so i thought i'd grab the divided clock and pipe it through the SERDES
<whitequark>
another option would be to have the other DCU or channel do something like output K28.3 on repeat at a much lower rate than the one i'm interested in
<whitequark>
if you want me to check anything specific re SERDES i can try!