22:05 <daveshah> Some very interesting info about FPGA testing in this Lattice PCN

22:05 <daveshah> http://www.latticesemi.com/view_document?document_id=52822

22:05 <daveshah> > Manufacturing speed testing is done using BIST approach called a Tpdcounter. The idea is to

22:05 <daveshah> the result of that oscillator into a counter.

22:05 <daveshah> create a ring oscillator that goes through as much of the FPGA fabric as possible and then feed

22:29 <adamgreig> i don't really get how they ended up with a yield of 1.01 in one instance

22:30 <daveshah> I think that means they ended up with too many high-speed-grade chips

22:43 <daveshah> Oh, just noticed this too

22:43 <daveshah> > 1. Generic DDRX1 modes were tested for error-free operation at 750, 1000, and 1300 Mb/s. No devices failed at any condition.

22:44 <daveshah> Not bad given they are officially rated for 500 Mb/s in that mode

22:45 <daveshah> Generally some useful info, JTAG port that's officially rated for 25MHz consistently exceeds 72MHz so I needn't feel guilty running running it at 40MHz

22:45 <sorear> yield > 1 is a hilarious concept

22:50 <sorear> oh, “normalized”

22:50 <cr1901_modern> So 1.01 == 1% better yield?